From: lkcl Date: Wed, 12 Apr 2023 19:19:21 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls010_v1~49 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=77301ed0884ed8e749d16c75f4791dc7c63fab44;p=libreriscv.git --- diff --git a/openpower/sv/rfc/ls011.mdwn b/openpower/sv/rfc/ls011.mdwn index 238cd125f..ef2d03828 100644 --- a/openpower/sv/rfc/ls011.mdwn +++ b/openpower/sv/rfc/ls011.mdwn @@ -1,5 +1,80 @@ -TODO +# LD/ST-Update-PostIncrement + +TODO (key stub notes below) * +The following instructions are proposed to be added in EXT2xx, +duplicating LD/ST-Update functionality but moving the update +of RA to *after* the Memory operation. These types of +instructions are already present in x86 (sort-of). + +* x86 chose that store should be pre-indexed and load should be post-indexed +* Power ISA chose everything to be pre-indexed + + + + +``` +# LD/ST-Postincrement +lbzup, ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W +lbzupx, ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W +lhzup, ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W +lhzupx, ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W +lhaup, ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W +lhaupx, ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W +lwzup, ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W +lwzupx, ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W +lwaupx, ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W +ldup, ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W +ldupx, ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W +stbup, ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W +stbupx, ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W +sthup, ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W +sthupx, ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W +stwup, ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W +stwupx, ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W +stdup, ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W +stdupx, ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W +# FP LD/ST-Postincrement +lfdu, ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W +lfsu, ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W +lfdux, ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W +lsdux, ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W +stfdu, ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W +stfsu, ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W +stfdux, ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W +stfsux, ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W +``` + +# Example + +** Load Byte and Zero with Post-Update** + +D-Form + +* lbzup RT,D(RA) + +Pseudo-code: + +``` + EA <- (RA) + RT <- ([0] * (XLEN-8)) || MEM(EA, 1) + RA <- (RA) + EXTS(D) +``` + +Special Registers Altered: + +``` + None +``` + +where the same pseudocode for `lbzu` is: + +``` + EA <- (RA) + EXTS(D) + RT <- ([0] * (XLEN-8)) || MEM(EA, 1) + RA <- EA +``` + [[!tag opf_rfc]]