From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 14 Apr 2022 10:24:17 +0000 (+0100)
Subject: add a dramsync2x domain as well
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7a1eed7b1a6f9be05ac9555e662ca79ea2566da2;p=ls2.git

add a dramsync2x domain as well
---

diff --git a/src/ls2.py b/src/ls2.py
index 708673b..6bee6d6 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -370,7 +370,12 @@ class DDR3SoC(SoC, Elaboratable):
             ddrmodule = dram_cls(clk_freq, "1:2") # match DDR3 ASIC P/N
 
             #drs = lambda x: x
-            drs = DomainRenamer("dramsync")
+            # remap both the sync domain (wherever it occurs) and
+            # the sync2x domain.  technically this should NOT be done.
+            # it's a bit of a mess.  ok: this should be done only
+            # when dramsync===sync (and dramsync2x===sync2x)
+            drs = DomainRenamer({"sync": "dramsync",
+                                 "sync2x": "dramsync2x"})
 
             if fpga == 'sim':
                 self.ddrphy = FakePHY(module=ddrmodule,