From: lkcl <lkcl@web>
Date: Sat, 2 Jul 2022 10:04:31 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1414
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7c33fa094b7d2b35eea49c0ebe010509b28ca243;p=libreriscv.git

---

diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index 60b8e2adc..50939b6b5 100644
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -127,8 +127,14 @@ There is considerable opcode pressure, consequently to set MVL and VL
 from different sources is as follows:
 
 | condition           | effect         |
-| - | |
-| `vf=1, RA=0, RT!=0` | VL set from CTR |
+| - | - |
+| `vf=1, RA=0, RT!=0` | VL,RT set to MIN(MVL, CTR)  |
+| `vf=1, RA=0, RT=0`  | VL set to MIN(MVL, SVi+1)  |
+| `vf=1, RA!=0, RT=0` | VL set to MIN(MVL, RA)  |
+| `vf=1, RA!=0, RT!=0` | VL,RT set to MIN(MVL, RA)  |
+
+The reasoning here is that the opportunity to set RT equal to the
+immediate `SVi+1` is sacrificed in favour of setting from CTR.
 
 # Vertical First Mode