From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 9 Jun 2021 15:50:54 +0000 (+0100)
Subject: sort out PLL connection, in and out of peripheral interconnect
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7d251f1b58cb3e1d5788645b4ce38286d6814c04;p=libresoc-litex.git

sort out PLL connection, in and out of peripheral interconnect
---

diff --git a/libresoc/core.py b/libresoc/core.py
index 6706a21..4ec36b0 100644
--- a/libresoc/core.py
+++ b/libresoc/core.py
@@ -186,7 +186,7 @@ class LibreSoC(CPU):
         self.platform     = platform
         self.variant      = variant
         self.reset        = Signal()
-        self.clk          = ClockSignal("cpu")
+        self.cpu_clk          = ClockSignal()
 
         irq_en = "noirq" not in variant
 
@@ -237,7 +237,7 @@ class LibreSoC(CPU):
 
         self.cpu_params = dict(
             # Clock / Reset
-            i_clk              = self.clk,
+            i_clk              = self.cpu_clk,
             i_rst              = ResetSignal() | self.reset,
 
             # Monitoring / Debugging
@@ -277,11 +277,13 @@ class LibreSoC(CPU):
             self.pll_vco_o = Signal()
             self.clk_sel = Signal(2)
             self.pll_test_o = Signal()
-            self.pllclk_o = Signal()
+            self.pll_24_i = Signal()
+            self.pllclk_o = ClockSignal("pll")
             self.cpu_params['i_clk_sel_i'] = self.clk_sel
+            self.cpu_params['i_clk_24_i'] = self.pll_24_i
             self.cpu_params['o_pll_vco_o'] = self.pll_vco_o
             self.cpu_params['o_pll_test_o'] = self.pll_test_o
-            self.cpu_params['o_pllclk_o'] = self.pllclk_o
+            self.cpu_params['o_pllclk_clk'] = self.pllclk_o
 
         # add wishbone buses to cpu params
         self.cpu_params.update(make_wb_bus("ibus", ibus, True))
diff --git a/libresoc/ls180.py b/libresoc/ls180.py
index 438982d..744e836 100644
--- a/libresoc/ls180.py
+++ b/libresoc/ls180.py
@@ -54,7 +54,7 @@ def make_gpio(name, num, n_gpio):
 def io():
     _io = [
         # CLK/RST: 2 pins
-        ("sys_clk", 0, Pins("G2"), IOStandard("LVCMOS33")),
+        ("sys_pllclk", 0, Pins("G2"), IOStandard("LVCMOS33")),
         ("sys_rst",   0, Pins("R1"), IOStandard("LVCMOS33")),
         ("sys_clksel_i",   0, Pins("R1 R2"), IOStandard("LVCMOS33")),
         ("sys_pll_testout_o",   0, Pins("R1"), IOStandard("LVCMOS33")),
diff --git a/ls180soc.py b/ls180soc.py
index 7836add..00606ed 100755
--- a/ls180soc.py
+++ b/ls180soc.py
@@ -6,7 +6,8 @@ from functools import reduce
 from operator import or_
 
 from migen import (Signal, FSM, If, Display, Finish, NextValue, NextState,
-                   Cat, Record, ClockSignal, wrap, ResetInserter)
+                   Cat, Record, ClockSignal, wrap, ResetInserter,
+                   ClockDomain, ResetSignal)
 
 from litex.build.generic_platform import Pins, Subsignal
 from litex.build.sim import SimPlatform
@@ -421,7 +422,10 @@ class LibreSoCSim(SoCCore):
                 self.bus.add_slave(name=name, slave=sram_wb, region=ics_region)
 
         # CRG -----------------------------------------------------------------
-        self.submodules.crg = CRG(platform.request("sys_clk"),
+        # power-on-reset still based on PLL, leave sys_rst HI until
+        # PLL stabilises
+        pll_clk = self.cpu.pllclk_o # PLL into cpu
+        self.submodules.crg = CRG(pll_clk,
                                   platform.request("sys_rst"))
 
         if hasattr(self.cpu, "clk_sel"):
@@ -433,8 +437,14 @@ class LibreSoCSim(SoCCore):
             self.comb += self.cpu.clk_sel.eq(clksel_i) # allow clock src select
             self.comb += pll_test_o.eq(self.cpu.pll_test_o) # "test" from PLL
             self.comb += pll_vco_o.eq(self.cpu.pll_vco_o) # PLL lock flag
-            cpu_clk = ClockDomain("cpu")
-            self.comb += cpu_clk.eq(self.cpu.pllclk_o) # PLL out into cpu
+            cd_cpu = ClockDomain()
+            cd_pll = ClockDomain("pll", reset_less=True)
+            self.clock_domains.cd_pll = cd_pll
+            sys_clk = platform.request("sys_pllclk") # incoming clock
+            self.comb += self.cpu.pll_24_i.eq(sys_clk)
+            self.comb += self.cd_pll.clk.eq(self.cpu.pllclk_o) # PLL into cpu
+            #self.comb += self.cd_cpu.rst.eq(ResetSignal())
+            #self.comb += self.cpu.cpu_clk.eq(cd_cpu.clk)
 
         #ram_init = []