From: Luke Kenneth Casson Leighton Date: Tue, 24 Apr 2018 10:53:32 +0000 (+0100) Subject: clarify X-Git-Tag: convert-csv-opcode-to-binary~5581 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=80fc819b2ae150c0e41c3032de17db4cafb2e0e0;p=libreriscv.git clarify --- diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn index 554d67f03..2f2402c88 100644 --- a/simple_v_extension.mdwn +++ b/simple_v_extension.mdwn @@ -478,7 +478,7 @@ register files: An array of 32 4-bit CSRs is needed (4 bits per register) to indicate whether a register was, if referred to in any standard instructions, -implicitly to be treated as a vector. +implicitly to be treated as a vector. Note: @@ -860,7 +860,7 @@ levels: Base and reserved future functionality. up to 16 (TBD) of either the floating-point or integer registers to be marked as "predicated" (key), and if so, which integer register to use as the predication mask (value). - + **TODO** # Implementing P (renamed to DSP) on top of Simple-V @@ -1605,9 +1605,9 @@ would still be there (and stalled). hmmm. > > Thrown away. -discussion then led to the question of OoO architectures +discussion then led to the question of OoO architectures -> The costs of the imprecise-exception model are greater than the benefit. +> The costs of the imprecise-exception model are greater than the benefit. > Software doesn't want to cope with it.  It's hard to debug.  You can't > migrate state between different microarchitectures--unless you force all > implementations to support the same imprecise-exception model, which would