From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 20 Jul 2018 08:00:40 +0000 (+0100)
Subject: add mk_connection
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=82ea3f1f9a26234b89a408bcf23b6406f5a43193;p=pinmux.git

add mk_connection
---

diff --git a/src/bsv/bsv_lib/slow_peripherals_template.bsv b/src/bsv/bsv_lib/slow_peripherals_template.bsv
index 7b6f2d9..8881af5 100644
--- a/src/bsv/bsv_lib/slow_peripherals_template.bsv
+++ b/src/bsv/bsv_lib/slow_peripherals_template.bsv
@@ -110,14 +110,7 @@ package slow_peripherals;
    	
 		mkConnection (bridge.axi4_lite_master,	slow_fabric.v_from_masters [0]);
 		/*======= Slave connections to AXI4Lite fabric =========*/
-		`ifdef UART0
-			mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(Uart0_slave_num))],	
-                    uart0.slave_axi_uart);  
-		`endif
-		`ifdef UART1
-	   	mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(Uart1_slave_num))],	
-                    uart1.slave_axi_uart); 
-		`endif
+{6}
 		`ifdef CLINT
 			mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(CLINT_slave_num))],
                     clint.axi4_slave);
@@ -126,14 +119,6 @@ package slow_peripherals;
 			mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(Plic_slave_num))],	
                     plic.axi4_slave_plic); //
 		`endif
-		`ifdef I2C0
-   		mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(I2c0_slave_num))],	
-                    i2c0.slave_i2c_axi); 
-		`endif
-		`ifdef I2C1
-   		mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(I2c1_slave_num))],		
-                    i2c1.slave_i2c_axi); // 
-		`endif
   		`ifdef QSPI0 
 			mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(Qspi0_slave_num))],	
                     qspi0.slave); 
diff --git a/src/bsv/peripheral_gen.py b/src/bsv/peripheral_gen.py
index 80c1b05..969c1ff 100644
--- a/src/bsv/peripheral_gen.py
+++ b/src/bsv/peripheral_gen.py
@@ -3,7 +3,8 @@ from copy import deepcopy
 
 
 class PBase(object):
-    pass
+    def __init__(self, name):
+        self.name = name
 
     def axibase(self, name, ifacenum):
         name = name.upper()
@@ -44,10 +45,22 @@ class PBase(object):
     def mkslow_peripheral(self):
         return ''
 
+    def mk_connection(self, count):
+        aname = self.axi_slave_name(self.name, count)
+        txt =  "        mkConnection (slow_fabric.v_to_slaves\n" + \
+               "                    [fromInteger(valueOf({1}))],\n" + \
+               "                    {0});"
+
+        con = self._mk_connection().format(count, aname)
+        if not con:
+            return ''
+        return txt.format(con, aname)
+
+    def _mk_connection(self):
+        return ''
+
 
 class uart(PBase):
-    def __init__(self):
-        PBase.__init__(self)
 
     def slowimport(self):
         return "          import Uart16550         :: *;"
@@ -64,10 +77,12 @@ class uart(PBase):
                "                mkUart16550(clocked_by uart_clock,\n" + \
                "                    reset_by uart_reset, sp_clock, sp_reset);"
 
+    def _mk_connection(self):
+        return "uart{0}.slave_axi_uart"
+
+
 
 class rs232(PBase):
-    def __init__(self):
-        PBase.__init__(self)
 
     def slowimport(self):
         return "        import Uart_bs::*;\n" + \
@@ -87,10 +102,11 @@ class rs232(PBase):
                "                mkUart_bs(clocked_by sp_clock,\n" + \
                "                    reset_by sp_reset, sp_clock, sp_reset);"
 
+    def _mk_connection(self):
+        return "uart{0}.slave_axi_uart"
+
 
 class twi(PBase):
-    def __init__(self):
-        PBase.__init__(self)
 
     def slowimport(self):
         return "        import I2C_top           :: *;"
@@ -105,10 +121,11 @@ class twi(PBase):
     def mkslow_peripheral(self):
         return "        I2C_IFC i2c{0} <- mkI2CController();"
 
+    def _mk_connection(self):
+        return "i2c{0}.slave_i2c_axi"
+
 
 class qspi(PBase):
-    def __init__(self):
-        PBase.__init__(self)
 
     def slowimport(self):
         return "        import qspi              :: *;"
@@ -123,10 +140,11 @@ class qspi(PBase):
     def mkslow_peripheral(self):
         return "        Ifc_qspi qspi{0} <-  mkqspi();"
 
+    def _mk_connection(self):
+        return "qspi{0}.slave"
+
 
 class pwm(PBase):
-    def __init__(self):
-        PBase.__init__(self)
 
     def slowimport(self):
         return "        import pwm::*;"
@@ -142,8 +160,6 @@ class pwm(PBase):
 
 
 class gpio(PBase):
-    def __init__(self):
-        PBase.__init__(self)
 
     def slowimport(self):
         return "     import pinmux::*;\n" + \
@@ -200,8 +216,9 @@ class PeripheralIface(object):
         self.slow = None
         slow = slowfactory.getcls(ifacename)
         if slow:
-            self.slow = slow()
-        for fname in ['slowimport', 'slowifdecl', 'mkslow_peripheral']:
+            self.slow = slow(ifacename)
+        for fname in ['slowimport', 'slowifdecl', 'mkslow_peripheral',
+                      'mk_connection']:
             fn = CallFn(self, fname)
             setattr(self, fname, types.MethodType(fn, self))
 
@@ -281,6 +298,14 @@ class PeripheralInterfaces(object):
                 ret.append(self.data[name].mkslow_peripheral().format(i))
         return '\n'.join(list(filter(None, ret)))
 
+    def mk_connection(self, *args):
+        ret = []
+        for (name, count) in self.ifacecount:
+            for i in range(count):
+                txt = self.data[name].mk_connection(i)
+                ret.append(txt)
+        return '\n'.join(list(filter(None, ret)))
+
 
 class PFactory(object):
     def getcls(self, name):
diff --git a/src/bsv/pinmux_generator.py b/src/bsv/pinmux_generator.py
index 70423ce..6a41b31 100644
--- a/src/bsv/pinmux_generator.py
+++ b/src/bsv/pinmux_generator.py
@@ -105,9 +105,10 @@ def write_slow(slow, template, p, ifaces):
     slavedecl = ifaces.axi_slave_idx()
     fnaddrmap = ifaces.axi_addr_map()
     mkslow = ifaces.mkslow_peripheral()
+    mkcon = ifaces.mk_connection()
     with open(slow, "w") as bsv_file:
         bsv_file.write(template.format(imports, ifdecl, regdef, slavedecl,
-                                       fnaddrmap, mkslow))
+                                       fnaddrmap, mkslow, mkcon))
 
 
 def write_bus(bus, p, ifaces):