From: Luke Kenneth Casson Leighton Date: Tue, 18 Jun 2019 12:39:46 +0000 (+0100) Subject: add separate read/write port X-Git-Tag: div_pipeline~1839 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=853a2ec703071117232ae0397700235a79ec6f2f;p=soc.git add separate read/write port --- diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py index 186108dc..11744db2 100644 --- a/src/experiment/score6600.py +++ b/src/experiment/score6600.py @@ -28,20 +28,27 @@ class TestMemory(Elaboratable): def __init__(self, regwid, addrw): self.ddepth = 1 # regwid //8 depth = (1<