From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 22 Jul 2019 03:39:03 +0000 (+0100)
Subject: fix imports
X-Git-Tag: ls180-24jan2020~787
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=85be6905a23f5b15da977e54429476c8b934d41a;p=ieee754fpu.git

fix imports
---

diff --git a/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py b/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py
index 28eacbd6..353ccc4f 100644
--- a/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py
+++ b/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py
@@ -2,8 +2,14 @@
 # See Notices.txt for copyright information
 """ div/rem/sqrt/rsqrt pipeline. """
 
-from .core import (DivPipeCoreConfig, DivPipeCoreInputData,
-                   DivPipeCoreInterstageData, DivPipeCoreOutputData)
+from ieee754.div_rem_sqrt_rsqrt.core import (DivPipeCoreConfig,
+                                             DivPipeCoreInputData,
+                                             DivPipeCoreInterstageData,
+                                             DivPipeCoreOutputData,
+                                             DivPipeCoreSetupStage,
+                                             DivPipeCoreCalculateStage,
+                                             DivPipeCoreFinalStage,
+                                            )
 from ieee754.fpcommon.getop import FPPipeContext
 from ieee754.fpcommon.fpbase import FPFormat, FPNumBaseRecord
 
@@ -61,7 +67,7 @@ class DivPipeBaseData:
 
     def eq(self, rhs):
         """ Assign member signals. """
-        return [self.z.eq(rhz.z, self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
+        return [self.z.eq(rhs.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
                 self.ctx.eq(i.ctx)]
 
 
diff --git a/src/ieee754/fpcommon/fpbase.py b/src/ieee754/fpcommon/fpbase.py
index 860d02dc..5f7df717 100644
--- a/src/ieee754/fpcommon/fpbase.py
+++ b/src/ieee754/fpcommon/fpbase.py
@@ -51,8 +51,6 @@ class FPFormat:
         :param width: bit-width of requested format.
         :returns: the requested ``FPFormat`` instance.
         """
-        if not instanceof(width, int):
-            raise TypeError()
         if width == 16:
             return FPFormat(5, 10)
         if width == 32:
diff --git a/src/ieee754/fpdiv/div0.py b/src/ieee754/fpdiv/div0.py
index 5f30d632..35cc41aa 100644
--- a/src/ieee754/fpdiv/div0.py
+++ b/src/ieee754/fpdiv/div0.py
@@ -92,7 +92,7 @@ class FPDivStage0Mod(Elaboratable):
                         ]
 
             m.d.comb += [self.o.z.e.eq(self.i.a.e - self.i.b.e + 1),
-                         self.o.z.s.eq(self.i.a.s ^ self.i.b.s)
+                         self.o.z.s.eq(self.i.a.s ^ self.i.b.s),
                          self.o.dividend.eq(am0), # TODO: check
                          self.o.divisor_radicand.eq(bm0), # TODO: check
                          self.o.operation.eq(Const(0)) # TODO check: DIV
diff --git a/src/ieee754/fpdiv/divstages.py b/src/ieee754/fpdiv/divstages.py
index e3b31d0d..6a65f005 100644
--- a/src/ieee754/fpdiv/divstages.py
+++ b/src/ieee754/fpdiv/divstages.py
@@ -74,7 +74,7 @@ class FPDivStagesSetup(FPState, SimpleHandshake):
         m.next = "normalise_1"
 
 
-class FPDivStagesIntermediary(FPState, SimpleHandshake):
+class FPDivStagesIntermediate(FPState, SimpleHandshake):
 
     def __init__(self, pspec, n_stages, stage_offs):
         FPState.__init__(self, "divintermediate")
diff --git a/src/ieee754/fpdiv/pipeline.py b/src/ieee754/fpdiv/pipeline.py
index 5bdbaf5f..4e483633 100644
--- a/src/ieee754/fpdiv/pipeline.py
+++ b/src/ieee754/fpdiv/pipeline.py
@@ -64,6 +64,7 @@ from nmutil.concurrentunit import ReservationStations, num_bits
 
 from ieee754.fpcommon.getop import FPADDBaseData
 from ieee754.fpcommon.denorm import FPSCData
+from ieee754.fpcommon.fpbase import FPFormat
 from ieee754.fpcommon.pack import FPPackData
 from ieee754.fpcommon.normtopack import FPNormToPack
 from ieee754.fpdiv.specialcases import FPDIVSpecialCasesDeNorm