From: Luke Kenneth Casson Leighton Date: Fri, 18 Feb 2022 11:53:06 +0000 (+0000) Subject: reduce TLB set size from 64 to 16 to get FPGA resource utilisation down X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=88a7bb476664778400e29a5c1b929fa9a2d74cd6;p=soc.git reduce TLB set size from 64 to 16 to get FPGA resource utilisation down --- diff --git a/Makefile b/Makefile index bdfa1f82..e89ad1d9 100644 --- a/Makefile +++ b/Makefile @@ -56,7 +56,9 @@ ls180_4k_verilog: --enable-xics --enable-sram4x4kblock --disable-svp64 \ src/soc/litex/florent/libresoc/libresoc.v -# build microwatt "external core" +# build microwatt "external core", note that the TLB set size is set to 16 +# for I/D-Cache which needs a corresponding alteration of the device-tree +# entries for linux microwatt_external_core: python3 src/soc/simple/issuer_verilog.py --microwatt-compat --enable-mmu \ external_core_top.v diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index 1c320ad9..0b74c4cd 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -197,7 +197,8 @@ class DCacheConfig: self.TLB_PTE_BITS = 64 self.TLB_PTE_WAY_BITS = self.TLB_NUM_WAYS * self.TLB_PTE_BITS; - assert (self.LINE_SIZE % self.ROW_SIZE) == 0, "LINE_SIZE not multiple of ROW_SIZE" + assert (self.LINE_SIZE % self.ROW_SIZE) == 0, \ + "LINE_SIZE not multiple of ROW_SIZE" assert ispow2(self.LINE_SIZE), "LINE_SIZE not power of 2" assert ispow2(self.NUM_LINES), "NUM_LINES not power of 2" assert ispow2(self.ROW_PER_LINE), "ROW_PER_LINE not power of 2" @@ -746,7 +747,8 @@ class DCache(Elaboratable, DCacheConfig): # reduce way sizes and num lines super().__init__(NUM_LINES = 16, NUM_WAYS = 1, - TLB_NUM_WAYS = 1) + TLB_NUM_WAYS = 1, + TLB_SET_SIZE=16) # XXX needs device-tree entry else: super().__init__() diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py index 25a5adb4..9e63f9ac 100644 --- a/src/soc/experiment/icache.py +++ b/src/soc/experiment/icache.py @@ -339,6 +339,7 @@ class ICache(FetchUnitInterface, Elaboratable, ICacheConfig): # reduce way sizes and num lines ICacheConfig.__init__(self, NUM_LINES = 4, NUM_WAYS = 1, + TLB_SIZE=16 # needs device-tree update ) else: ICacheConfig.__init__(self)