From: Luke Kenneth Casson Leighton Date: Tue, 24 Apr 2018 08:03:14 +0000 (+0100) Subject: spelling X-Git-Tag: convert-csv-opcode-to-binary~5591 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=88ee87d63756893a51af5d1d59d20a9fc8d6e5da;p=libreriscv.git spelling --- diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn index d70038747..b4f155352 100644 --- a/simple_v_extension.mdwn +++ b/simple_v_extension.mdwn @@ -211,10 +211,10 @@ Interestingly, none of this complexity is faced in SIMD architectures... but then they do not get the opportunity to optimise for highly-streamlined memory accesses either. -With the "bang-per-buck" ratio being so high and the direct improvement -in L1 Instruction Cache usage, as well as the opportunity to optimise -L1 and L2 cache usage, the case for including Vector LOAD/STORE is -compelling. +With the "bang-per-buck" ratio being so high and the indirect improvement +in L1 Instruction Cache usage (reduced instruction count), as well as +the opportunity to optimise L1 and L2 cache usage, the case for including +Vector LOAD/STORE is compelling. ## Mask and Tagging (Predication)