From: Luke Kenneth Casson Leighton Date: Wed, 15 Jul 2020 14:20:59 +0000 (+0100) Subject: move priv test to above illegal/trap test X-Git-Tag: div_pipeline~23 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8a0e6a5c59e4af9027685a45e8854e178544b4cb;p=soc.git move priv test to above illegal/trap test --- diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index 8cc68f4f..5ae286e5 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -679,11 +679,16 @@ class PowerDecode2(Elaboratable): with m.If(op.internal_op == MicrOp.OP_TRAP): comb += do.trapaddr.eq(0x70) # addr=0x700 (strip first nibble) + # TODO: get msr, then can do privileged instruction + with m.If(instr_is_priv(m, op.internal_op, e.do.insn) & msr[MSR.PR]): + # privileged instruction trap + self.trap(m, TT_PRIV, 0x700) + # illegal instruction must redirect to trap. this is done by # *overwriting* the decoded instruction and starting again. # (note: the same goes for interrupts and for privileged operations, # just with different trapaddr and traptype) - with m.If(op.internal_op == MicrOp.OP_ILLEGAL): + with m.Elif(op.internal_op == MicrOp.OP_ILLEGAL): # illegal instruction trap self.trap(m, TT_ILLEG, 0x700) @@ -707,11 +712,6 @@ class PowerDecode2(Elaboratable): comb += e.read_fast2.data.eq(FastRegs.SRR1) # constant: SRR1 comb += e.read_fast2.ok.eq(1) - # TODO: get msr, then can do privileged instruction - with m.If(instr_is_priv(m, op.internal_op, e.do.insn) & msr[MSR.PR]): - # privileged instruction trap - self.trap(m, TT_PRIV, 0x700) - return m def trap(self, m, traptype, trapaddr):