From: Luke Kenneth Casson Leighton Date: Sun, 19 Dec 2021 15:54:15 +0000 (+0000) Subject: set terminate if core terminate requested X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8c0a56c349b0d5650026e0ce9031272104cdc39a;p=soc.git set terminate if core terminate requested rather than override what is in TestIssuerBase, which examines PC for a DBG DMI Halt condition (stop_addr_o) --- diff --git a/src/soc/simple/inorder.py b/src/soc/simple/inorder.py index 510bd2da..4edf92f1 100644 --- a/src/soc/simple/inorder.py +++ b/src/soc/simple/inorder.py @@ -435,7 +435,8 @@ class TestIssuerInternalInOrder(TestIssuerBase): nia = Signal(64) # connect up debug signals - comb += dbg.terminate_i.eq(core.o.core_terminate_o) + with m.If(core.o.core_terminate_o): + comb += dbg.terminate_i.eq(1) # there are *THREE^WFOUR-if-SVP64-enabled* FSMs, fetch (32/64-bit) # issue, decode/execute, now joined by "Predicate fetch/calculate". diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index 15391fe8..156fce3c 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -1415,7 +1415,8 @@ class TestIssuerInternal(TestIssuerBase): nia = Signal(64) # connect up debug signals - comb += dbg.terminate_i.eq(core.o.core_terminate_o) + with m.If(core.o.core_terminate_o): + comb += dbg.terminate_i.eq(1) # pass the prefix mode from Fetch to Issue, so the latter can loop # on VL==0