From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 4 May 2022 14:11:23 +0000 (+0100)
Subject: pass in freq setting to nextpnr-xilinx
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8c6c0f3f1ff1e97e95996e711aa416d2b3c38977;p=ls2.git

pass in freq setting to nextpnr-xilinx
also allow timing fail
---

diff --git a/src/ls2.py b/src/ls2.py
index 493442b..4ab93f9 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -871,7 +871,7 @@ def build_platform(fpga, firmware):
         clk_freq = 50e6
         dram_clk_freq = 100e6
     if fpga == 'arty_a7':
-        clk_freq = 25.0e6 # urrr "working" with the QSPI core (25 mhz does not)
+        clk_freq = 27.0e6 # urrr "working" with the QSPI core (25 mhz does not)
     if fpga == 'ulx3s':
         clk_freq = 40.0e6
     if fpga == 'orangecrab':
@@ -1106,7 +1106,9 @@ def build_platform(fpga, firmware):
 
     if toolchain == 'yosys_nextpnr':
         # add --seed 2 to arty a7 compile-time options
-        os.environ['NMIGEN_nextpnr_opts'] = '--seed 1'
+        freq = clk_freq/1e6
+        os.environ['NMIGEN_nextpnr_opts'] = '--seed 3 --freq %.1f' % freq
+        os.environ['NMIGEN_nextpnr_opts'] += ' --timing-allow-fail'
 
     if platform is not None:
         # build and upload it