From: Cesar Strauss Date: Sun, 1 Jan 2023 12:30:41 +0000 (-0300) Subject: Handle newer nMigen adding a "bench" hierarchy root in VCD files X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8e00e09b914b9fa3af430c2f913a9921207063cd;p=soc.git Handle newer nMigen adding a "bench" hierarchy root in VCD files --- diff --git a/src/soc/experiment/test/test_compalu_multi.py b/src/soc/experiment/test/test_compalu_multi.py index 39b24147..2f2c51d1 100644 --- a/src/soc/experiment/test/test_compalu_multi.py +++ b/src/soc/experiment/test/test_compalu_multi.py @@ -534,14 +534,14 @@ def test_compunit_fsm(): 'n_data_o[7:0]', ({'submodule': 'n'}, ['n_o_valid', 'n_i_ready'])])]), - ('debug', {'module': 'top'}, + ('debug', {'module': 'bench'}, ['src1_count[7:0]', 'src2_count[7:0]', 'dest1_count[7:0]'])] write_gtkw( "test_compunit_fsm1.gtkw", "test_compunit_fsm1.vcd", traces, style, - module='top.cu' + module='bench.top.cu' ) m = Module() alu = Shifter(8) @@ -667,7 +667,7 @@ def test_compunit_regspec3(): "test_compunit_regspec3.vcd", traces, style, clk_period=1e-6, - module='top.cu') + module='bench.top.cu') inspec = [('INT', 'a', '0:15'), ('INT', 'b', '0:15'), @@ -738,14 +738,14 @@ def test_compunit_regspec1(): ('next port', 'out', [ 'alu_o[15:0]', 'o_valid', 'i_ready', 'alu_o_ok', 'alu_cr_ok'])]), - ('debug', {'module': 'top'}, + ('debug', {'module': 'bench'}, ['src1_count[7:0]', 'src2_count[7:0]', 'dest1_count[7:0]'])] write_gtkw("test_compunit_regspec1.gtkw", "test_compunit_regspec1.vcd", traces, style, clk_period=1e-6, - module='top.cu') + module='bench.top.cu') inspec = [('INT', 'a', '0:15'), ('INT', 'b', '0:15')]