From: Tim Newsome Date: Sun, 1 May 2016 20:18:03 +0000 (-0700) Subject: Implement single memory read access. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8e418f9e54a3a0d8f15b75ad1ad43ae925fea7e0;p=riscv-isa-sim.git Implement single memory read access. Prevent unaligned accesses in memory read. Also change how exceptions in Debug Mode are signaled. --- diff --git a/debug_rom/debug_rom.S b/debug_rom/debug_rom.S index b1fa8bd..35dd406 100755 --- a/debug_rom/debug_rom.S +++ b/debug_rom/debug_rom.S @@ -29,15 +29,14 @@ entry: j _entry resume: j _resume exception: - # Flip the LSB of the first word in Debug RAM so the debugger can know - # that we hit an exception. - lw s1, (DEBUG_RAM)(zero) - xori s1, s1, 1 - sw s1, (DEBUG_RAM)(zero) - - # Fall through to resume. + # Set the last word of Debug RAM to all ones, to indicate that we hit + # an exception. + li s0, ~0 + j _resume2 _resume: + li s0, 0 +_resume2: # Clear debug interrupt. csrr s1, CSR_MHARTID sw s1, CLEARDEBINT(zero) @@ -58,6 +57,11 @@ restore_64: restore_128: nop #lq s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 16)(zero) + # s0 contains ~0 if we got here through an exception, and 0 otherwise. + # Store this to the last word in Debug RAM so the debugger can tell if + # an exception occurred. + sw s0, (DEBUG_RAM + DEBUG_RAM_SIZE - 4)(zero) + check_halt: csrr s0, DCSR andi s0, s0, (1<> 32); + gs.set_interrupt(0); + + gs.start_packet(); + + return false; + } + + bool step() + { + char buffer[3]; + reg_t value = ((uint64_t) gs.read_debug_ram(7) << 32) | gs.read_debug_ram(6); + for (unsigned int i = 0; i < access_size; i++) { + sprintf(buffer, "%02x", (unsigned int) (value & 0xff)); + gs.send(buffer); + value >>= 8; + } + length -= access_size; + addr += access_size; + + if (length == 0) { + gs.end_packet(); + return true; + } else { + gs.write_debug_ram(4, addr); + gs.write_debug_ram(5, addr >> 32); + gs.set_interrupt(0); + return false; + } + } + + private: + reg_t addr; + unsigned int length; + unsigned int access_size; +}; + ////////////////////////////// gdbserver itself gdbserver_t::gdbserver_t(uint16_t port, sim_t *sim) : @@ -764,16 +858,7 @@ void gdbserver_t::handle_memory_read(const std::vector &packet) if (*iter != '#') return send_packet("E11"); - start_packet(); - char buffer[3]; - processor_t *p = sim->get_core(0); - mmu_t* mmu = sim->debug_mmu; - - for (reg_t i = 0; i < length; i++) { - sprintf(buffer, "%02x", mmu->load_uint8(address + i)); - send(buffer); - } - end_packet(); + set_operation(new memory_read_op_t(*this, address, length)); } void gdbserver_t::handle_memory_binary_write(const std::vector &packet) diff --git a/riscv/processor.cc b/riscv/processor.cc index 7f3ba42..f09eea8 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -206,9 +206,13 @@ void processor_t::enter_debug_mode(uint8_t cause) void processor_t::take_trap(trap_t& t, reg_t epc) { - if (debug) + if (debug) { fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n", id, t.name(), epc); + if (t.has_badaddr()) + fprintf(stderr, "core %3d: badaddr 0x%016" PRIx64 "\n", id, + t.get_badaddr()); + } if (t.cause() == CAUSE_BREAKPOINT && sim->gdbserver && sim->gdbserver->connected()) {