From: Megan Wachs <megan@sifive.com>
Date: Thu, 9 Nov 2017 01:18:02 +0000 (-0800)
Subject: Merge pull request #46 from sifive/gpio_iof_pueds
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9052a079d404ebbfda5f01765b909c20503504ad;hp=d1d2f47f609638c43546d4a9d0a4018c73dee4bb;p=sifive-blocks.git

Merge pull request #46 from sifive/gpio_iof_pueds

GPIO: IOF should not override PUE and DS
---

diff --git a/src/main/scala/devices/gpio/GPIO.scala b/src/main/scala/devices/gpio/GPIO.scala
index f598dbb..f5098cf 100644
--- a/src/main/scala/devices/gpio/GPIO.scala
+++ b/src/main/scala/devices/gpio/GPIO.scala
@@ -168,10 +168,10 @@ trait HasGPIOModuleContents extends MultiIOModule with HasRegMap {
   val swPinCtrl = Wire(Vec(c.width, new EnhancedPinCtrl()))
 
   // This strips off the valid.
-  val iof0Ctrl = Wire(Vec(c.width, new EnhancedPinCtrl()))
-  val iof1Ctrl = Wire(Vec(c.width, new EnhancedPinCtrl()))
+  val iof0Ctrl = Wire(Vec(c.width, new IOFCtrl()))
+  val iof1Ctrl = Wire(Vec(c.width, new IOFCtrl()))
 
-  val iofCtrl = Wire(Vec(c.width, new EnhancedPinCtrl()))
+  val iofCtrl = Wire(Vec(c.width, new IOFCtrl()))
   val iofPlusSwPinCtrl = Wire(Vec(c.width, new EnhancedPinCtrl()))
 
   for (pin <- 0 until c.width) {