From: Christopher Celio Date: Tue, 15 Sep 2015 22:05:11 +0000 (-0700) Subject: Zero-extend flw, fmv_s_x instructions X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=95d49c1d512e87a36107c31fb0c0598a2554751b;p=riscv-isa-sim.git Zero-extend flw, fmv_s_x instructions - This makes Spike more consistent with its zero-extending behavior regarding other SP operations when placed into the 64b f-registers. --- diff --git a/riscv/insns/flw.h b/riscv/insns/flw.h index b94ba5d..489e743 100644 --- a/riscv/insns/flw.h +++ b/riscv/insns/flw.h @@ -1,3 +1,3 @@ require_extension('F'); require_fp; -WRITE_FRD(MMU.load_int32(RS1 + insn.i_imm())); +WRITE_FRD(MMU.load_uint32(RS1 + insn.i_imm())); diff --git a/riscv/insns/fmv_s_x.h b/riscv/insns/fmv_s_x.h index f0f95ac..2daf6da 100644 --- a/riscv/insns/fmv_s_x.h +++ b/riscv/insns/fmv_s_x.h @@ -1,3 +1,3 @@ require_extension('F'); require_fp; -WRITE_FRD(RS1); +WRITE_FRD(zext32(RS1));