From: colepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0 <colepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0@web>
Date: Sun, 1 Nov 2020 22:23:40 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1889
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=997a9b5799e9fda603017b8a755095ed5eafe6d0;p=libreriscv.git

---

diff --git a/HDL_workflow/fpga.mdwn b/HDL_workflow/fpga.mdwn
index 47ffe9aa1..d62fe95e5 100644
--- a/HDL_workflow/fpga.mdwn
+++ b/HDL_workflow/fpga.mdwn
@@ -151,7 +151,7 @@ and therefore have no value are marked with 'NOT'
 
 ## Images of wires on FPGA and on STLINKV2
 
-pic fpga                                     pic stlinkv2
+[[!img HDL_workflow/jtag_wires_ulx3s_fpga.jpg size="200x" ]] [[!img HDL_workflow/jtag_wires_ulx3s_stlinkv2.jpg size="400x" ]]                                    
 
 ## Questions