From: Robin Ole Heinemann Date: Sat, 2 Jan 2021 23:17:48 +0000 (+0100) Subject: lib.fifo.AsyncFIFOBuffered: fix output register accounting X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9af820172793738ad07cf2225a3d9e14e7ddadb4;p=nmigen.git lib.fifo.AsyncFIFOBuffered: fix output register accounting --- diff --git a/nmigen/lib/fifo.py b/nmigen/lib/fifo.py index ceb254d..0cab225 100644 --- a/nmigen/lib/fifo.py +++ b/nmigen/lib/fifo.py @@ -509,7 +509,7 @@ class AsyncFIFOBuffered(Elaboratable, FIFOInterface): ] r_consume_buffered = Signal() - m.d.comb += r_consume_buffered.eq(self.r_rdy - self.r_en) + m.d.comb += r_consume_buffered.eq((self.r_rdy - self.r_en) & self.r_rdy) m.d[self._r_domain] += self.r_level.eq(fifo.r_level + r_consume_buffered) w_consume_buffered = Signal() diff --git a/tests/test_lib_fifo.py b/tests/test_lib_fifo.py index f2edf30..0e322c1 100644 --- a/tests/test_lib_fifo.py +++ b/tests/test_lib_fifo.py @@ -305,7 +305,7 @@ class AsyncFIFOSimCase(FHDLTestCase): simulator.add_sync_process(testbench) simulator.run() - def check_async_fifo_level(self, fifo, fill_in, expected_level): + def check_async_fifo_level(self, fifo, fill_in, expected_level, read=False): write_done = Signal() def write_process(): @@ -320,6 +320,8 @@ class AsyncFIFOSimCase(FHDLTestCase): yield write_done.eq(1) def read_process(): + if read: + yield fifo.r_en.eq(1) while not (yield write_done): yield Tick("read") self.assertEqual((yield fifo.r_level), expected_level) @@ -351,3 +353,7 @@ class AsyncFIFOSimCase(FHDLTestCase): def test_async_buffered_fifo_level_full(self): fifo = AsyncFIFOBuffered(width=32, depth=9, r_domain="read", w_domain="write") self.check_async_fifo_level(fifo, fill_in=10, expected_level=9) + + def test_async_buffered_fifo_level_empty(self): + fifo = AsyncFIFOBuffered(width=32, depth=9, r_domain="read", w_domain="write") + self.check_async_fifo_level(fifo, fill_in=0, expected_level=0, read=True)