From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 23 Jul 2019 09:15:51 +0000 (+0100)
Subject: add some voodoo magic extra bits on the input numbers in fpdiv
X-Git-Tag: ls180-24jan2020~759
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9bbdef1c6988966c27cc0a70176be34c1114cce1;p=ieee754fpu.git

add some voodoo magic extra bits on the input numbers in fpdiv
---

diff --git a/src/ieee754/fpdiv/div0.py b/src/ieee754/fpdiv/div0.py
index 80ffc689..87355332 100644
--- a/src/ieee754/fpdiv/div0.py
+++ b/src/ieee754/fpdiv/div0.py
@@ -55,11 +55,24 @@ class FPDivStage0Mod(Elaboratable):
             # into DivPipeInputData dividend and divisor.
 
             if self.pspec.width == 16:
-                extra = 3
+                if self.pspec.log2_radix == 1:
+                    extra = 2
+                elif self.pspec.log2_radix == 3:
+                    extra = 2
+                else:
+                    extra = 3
             elif self.pspec.width == 32:
-                extra = 4
+                if self.pspec.log2_radix == 1:
+                    extra = 3
+                else:
+                    extra = 4
             elif self.pspec.width == 64:
-                extra = 3
+                if self.pspec.log2_radix == 1:
+                    extra = 2
+                elif self.pspec.log2_radix == 3:
+                    extra = 2
+                else:
+                    extra = 3
             # the mantissas, having been de-normalised (and containing
             # a "1" in the MSB) represent numbers in the range 0.5 to
             # 0.9999999-recurring.  the min and max range of the
diff --git a/src/ieee754/fpdiv/pipeline.py b/src/ieee754/fpdiv/pipeline.py
index cf2a04c2..553af107 100644
--- a/src/ieee754/fpdiv/pipeline.py
+++ b/src/ieee754/fpdiv/pipeline.py
@@ -81,13 +81,13 @@ class FPDIVBasePipe(ControlBase):
         ControlBase.__init__(self)
 
         pipechain = []
-        n_comb_stages = 3  # TODO (depends on how many RS's we want)
         # to which the answer: "as few as possible"
         # is required.  too many ReservationStations
         # means "big problems".
 
         # get number of stages, set up loop.
         n_stages = pspec.core_config.n_stages
+        n_comb_stages = self.pspec.n_comb_stages
         print ("n_stages", n_stages)
         stage_idx = 0
 
@@ -157,7 +157,8 @@ class FPDIVMuxInOut(ReservationStations):
         self.pspec = PipelineSpec(width, self.id_wid, op_wid)
         # get the standard mantissa width, store in the pspec HOWEVER...
         fmt = FPFormat.standard(width)
-        log2_radix = 2
+        log2_radix = 3     # tested options so far: 1, 2 and 3.
+        n_comb_stages = 3  # TODO (depends on how many RS's we want)
 
         # ...5 extra bits on the mantissa: MSB is zero, MSB-1 is 1
         # then there is guard, round and sticky at the LSB end.
@@ -175,6 +176,7 @@ class FPDIVMuxInOut(ReservationStations):
 
         self.pspec.fpformat = fmt
         self.pspec.log2_radix = log2_radix
+        self.pspec.n_comb_stages = n_comb_stages
         self.pspec.core_config = cfg
 
         # XXX TODO - a class (or function?) that takes the pspec (right here)