From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 17 Jun 2018 13:36:40 +0000 (+0100)
Subject: add slides
X-Git-Tag: convert-csv-opcode-to-binary~5177
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9d271a8e7fa7e103f88b57740e837c5741670eee;p=libreriscv.git

add slides
---

diff --git a/pinmux/pinmux_chennai_2018.tex b/pinmux/pinmux_chennai_2018.tex
index 7b9b9504d..2b1bd5537 100644
--- a/pinmux/pinmux_chennai_2018.tex
+++ b/pinmux/pinmux_chennai_2018.tex
@@ -121,9 +121,9 @@
 	     BSV (Bluespec), Verilog, VHDL, MyHDL.
 		 \vspace{10pt}
    \item Multiple auto-generated code-formats permits cross-validation:\\
-	     different areas of expertise bootstraps others
+	     auto-generated test suite in one HDL can validate a muxer
+	     generated for a different target HDL.
    		 \vspace{10pt}
-		  
   \end{itemize}
 }