From: Tobias Platen <tplaten@posteo.de>
Date: Sun, 25 Aug 2019 17:31:34 +0000 (+0200)
Subject: forgot to add one signal
X-Git-Tag: div_pipeline~1827
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9ff95a317ae379ec9aea16e4637a2fedc44f266c;p=soc.git

forgot to add one signal
---

diff --git a/src/TLB/ariane/ptw.py b/src/TLB/ariane/ptw.py
index 706d6518..ce8c774f 100644
--- a/src/TLB/ariane/ptw.py
+++ b/src/TLB/ariane/ptw.py
@@ -451,6 +451,7 @@ class PTW(Elaboratable):
 
         l1err = Signal(reset_less=True)
         l2err = Signal(reset_less=True)
+        l3err = Signal(reset_less=True)
         m.d.comb += [l3err.eq((ptw_lvl3) & pte.ppn[0:9] != Const(0,0)),
                      l2err.eq((ptw_lvl2) & pte.ppn[0:18] != Const(0, 18)),
                      l1err.eq((ptw_lvl1) & pte.ppn[0:27] != Const(0, 27))]
diff --git a/src/TLB/ariane/test/test_tlb.py b/src/TLB/ariane/test/test_tlb.py
index e10325f8..b94438ff 100644
--- a/src/TLB/ariane/test/test_tlb.py
+++ b/src/TLB/ariane/test/test_tlb.py
@@ -67,3 +67,4 @@ def tbench(dut):
 if __name__ == "__main__":
     dut = TLB()
     run_simulation(dut, tbench(dut), vcd_name="test_tlb.vcd")
+    print("TLB Unit Test Success")