From: Luke Kenneth Casson Leighton Date: Sat, 5 Jun 2021 18:30:08 +0000 (+0100) Subject: use git submodule soclayout for source files, rather than X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=HEAD;p=soc-cocotb-sim.git use git submodule soclayout for source files, rather than commit (yet another) copy of an auto-generated file TODO: replace all other duplicated copies of additional files, there are now half a dozen copies of pll.v for example --- diff --git a/.gitmodules b/.gitmodules index 663524b..ba7ad5b 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,6 @@ [submodule "alliance-check-toolkit"] path = alliance-check-toolkit url = https://gitlab.lip6.fr/vlsi-eda/alliance-check-toolkit.git +[submodule "soclayout"] + path = soclayout + url = git://libre-soc.org/soclayout.git diff --git a/ls180/experiment9_recon/Makefile b/ls180/experiment9_recon/Makefile index 68efc45..9942b9c 100644 --- a/ls180/experiment9_recon/Makefile +++ b/ls180/experiment9_recon/Makefile @@ -9,8 +9,7 @@ TOPLEVEL_LANG := verilog VERILOG_SOURCES := \ ../spblock_512w64b8w.v \ ../pll.v \ - full_core_4_4ksram_libresoc_recon.v \ - full_core_4_4ksram_litex_ls180_recon.v \ + ls180.v # END VERILOG_SOURCES MODULE := test diff --git a/ls180/experiment9_recon/run_iverilog_ls180.sh b/ls180/experiment9_recon/run_iverilog_ls180.sh index eae0986..9dba6e6 100755 --- a/ls180/experiment9_recon/run_iverilog_ls180.sh +++ b/ls180/experiment9_recon/run_iverilog_ls180.sh @@ -1,5 +1,11 @@ #!/bin/sh +SRCDIR=../../soclayout/experiments9/non_generated/ +cp $SRCDIR/full_core_4_4ksram_litex_ls180_recon.v litex_ls180.v +cp $SRCDIR/full_core_4_4ksram_libresoc_recon.v libresoc.v +cp $SRCDIR/pll.v . +cp $SRCDIR/ls180.v . + touch mem.init mem_1.init mem_2.init mem_3.init mem_4.init # Only run test in reset state as running CPU takes too much time to simulate make \ diff --git a/soclayout b/soclayout new file mode 160000 index 0000000..4f3fce3 --- /dev/null +++ b/soclayout @@ -0,0 +1 @@ +Subproject commit 4f3fce32074946c452fe9089cec271a6d5843e59