From: Luke Kenneth Casson Leighton Date: Fri, 26 Oct 2018 21:16:53 +0000 (+0100) Subject: extend addw bitwidth test to 3 registers X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a11b75d5e780733325a53e13a665c79719ad49c9;p=riscv-tests.git extend addw bitwidth test to 3 registers --- diff --git a/isa/rv64ui/sv_addw_elwidth.S b/isa/rv64ui/sv_addw_elwidth.S index 370e341..fad659d 100644 --- a/isa/rv64ui/sv_addw_elwidth.S +++ b/isa/rv64ui/sv_addw_elwidth.S @@ -3,32 +3,36 @@ RVTEST_RV64U # Define TVM used by program. -#define SV_ELWIDTH_TEST( wid1, wid2, wid3, expect1, expect2 ) \ +#define SV_ELWIDTH_TEST( wid1, wid2, wid3, expect1, expect2, expect3 ) \ \ - SV_LDD_DATA( x4, testdata , 0); \ - SV_LDD_DATA( x5, testdata+8 , 0); \ - SV_LDD_DATA( x12, testdata+16, 0); \ - SV_LDD_DATA( x13, testdata+24, 0); \ + SV_LDD_DATA( x12, testdata , 0); \ + SV_LDD_DATA( x13, testdata+8 , 0); \ + SV_LDD_DATA( x14, testdata+16, 0); \ + SV_LDD_DATA( x15, testdata+24, 0); \ + SV_LDD_DATA( x16, testdata+32, 0); \ + SV_LDD_DATA( x17, testdata+40, 0); \ \ - li x14, 0xa5a5a5a5a5a5a5a5; \ - li x15, 0xa5a5a5a5a5a5a5a5; \ + li x28, 0xa5a5a5a5a5a5a5a5; \ + li x29, 0xa5a5a5a5a5a5a5a5; \ + li x30, 0xa5a5a5a5a5a5a5a5; \ \ - SET_SV_MVL( 2); \ - SET_SV_3CSRS( SV_REG_CSR( 1, 4, wid1, 4, 1), \ + SET_SV_MVL( 3); \ + SET_SV_3CSRS( SV_REG_CSR( 1, 15, wid1, 15, 1), \ SV_REG_CSR( 1, 12, wid2, 12, 1), \ - SV_REG_CSR( 1, 14, wid3, 14, 1)); \ - SET_SV_VL( 2); \ + SV_REG_CSR( 1, 28, wid3, 28, 1)); \ + SET_SV_VL( 3); \ \ - addw x14, x4, x12; \ + addw x28, x15, x12; \ \ CLR_SV_CSRS(); \ SET_SV_VL( 1); \ SET_SV_MVL( 1); \ \ - TEST_SV_IMM( x14, expect1 ); \ - TEST_SV_IMM( x15, expect2 ); \ - TEST_SV_IMM( x12, 0x0000005242322212); \ - TEST_SV_IMM( x13, 0x0000005141312111); + TEST_SV_IMM( x28, expect1 ); \ + TEST_SV_IMM( x29, expect2 ); \ + TEST_SV_IMM( x30, expect3 ); \ + TEST_SV_IMM( x15, 0x0000005242322212); \ + TEST_SV_IMM( x16, 0x0000005141312111); # SV test: vector-vector add @@ -40,12 +44,18 @@ RVTEST_RV64U # Define TVM used by program. RVTEST_CODE_BEGIN # Start of test code. # - SV_ELWIDTH_TEST( 0, 0, 0, 0xffffffff8b6bab8b, 0xffffffff88684828 ) - SV_ELWIDTH_TEST( 0, 0, 3, 0x886848288b6bab8b, 0xa5a5a5a5a5a5a5a5 ) - SV_ELWIDTH_TEST( 1, 1, 0, 0xffffffffffffff8b, 0xffffffffffffffab ) - SV_ELWIDTH_TEST( 1, 1, 3, 0xffffffabffffff8b, 0xa5a5a5a5a5a5a5a5 ) - SV_ELWIDTH_TEST( 1, 1, 2, 0xa5a5a5a5ffabff8b, 0xa5a5a5a5a5a5a5a5 ) - SV_ELWIDTH_TEST( 1, 1, 1, 0xa5a5a5a5a5a5ab8b, 0xa5a5a5a5a5a5a5a5 ) + SV_ELWIDTH_TEST( 0, 0, 0, + 0xffffffff8b6bab8b, 0xffffffff88684828, 0x0000000000000000 ) + SV_ELWIDTH_TEST( 0, 0, 3, + 0x886848288b6bab8b, 0xa5a5a5a500000000, 0xa5a5a5a5a5a5a5a5 ) + SV_ELWIDTH_TEST( 1, 1, 0, + 0xffffffffffffff8b, 0xffffffffffffffab, 0x000000000000006b ) + SV_ELWIDTH_TEST( 1, 1, 3, + 0xffffffabffffff8b, 0xa5a5a5a50000006b, 0xa5a5a5a5a5a5a5a5 ) + SV_ELWIDTH_TEST( 1, 1, 2, + 0xa5a5006bffabff8b, 0xa5a5a5a5a5a5a5a5, 0xa5a5a5a5a5a5a5a5 ) + SV_ELWIDTH_TEST( 1, 1, 1, + 0xa5a5a5a5a56bab8b, 0xa5a5a5a5a5a5a5a5, 0xa5a5a5a5a5a5a5a5 ) RVTEST_PASS # Signal success. fail: @@ -59,8 +69,10 @@ RVTEST_CODE_END # End of test code. testdata: .dword 0x0000005949398979 .dword 0x0000005747372717 + .dword 0x0000000000000000 .dword 0x0000005242322212 .dword 0x0000005141312111 + .dword 0x0000000000000000 # Output data section. RVTEST_DATA_BEGIN # Start of test output data region.