From: lkcl <lkcl@web>
Date: Wed, 17 Mar 2021 13:23:14 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~7
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a31d6c35795ff6a3be70c1899130e708272fad42;p=libreriscv.git

---

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index 1ed3ff82f..bf82f88cd 100644
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -20,6 +20,7 @@ Links:
 * <https://bugs.libre-soc.org/show_bug.cgi?id=587> setvl ancillary tasks
  (instruction form SVL-Form, field designations, pseudocode, SPR allocation)
 * <https://bugs.libre-soc.org/show_bug.cgi?id=615> agree sv assembly syntax
+* <https://bugs.libre-soc.org/show_bug.cgi?id=617> TestIssuer add single/twin Predication
 
 # Code to convert
 
@@ -184,9 +185,9 @@ TODO.  INTs, FPs, CRs, these all increase to 128.  Welcome To Vector ISAs.
 
 At the same time the `Rc=1` CR offsets normslly CR0 and CR1 for fixed and FP scalar may also be adjusted.
 
-## Single Predication
+## Single and Twin Predication
 
-TODO
+* <https://bugs.libre-soc.org/show_bug.cgi?id=617> TestIssuer 
 
 ## Element width overrides