From: Andrew Waterman <waterman@s144.Millennium.Berkeley.EDU>
Date: Tue, 5 Oct 2010 22:08:18 +0000 (-0700)
Subject: [xcc,sim] eliminated vectored traps
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a359d7b81adb7f1ca371822bd2df3bac7cda99ba;p=riscv-isa-sim.git

[xcc,sim] eliminated vectored traps

now, the evec register holds the address that all traps vector to,
and the cause register is set with the trap number.
---

diff --git a/riscv/insns/mfpcr.h b/riscv/insns/mfpcr.h
index 0060957..704e37b 100644
--- a/riscv/insns/mfpcr.h
+++ b/riscv/insns/mfpcr.h
@@ -14,7 +14,7 @@ switch(insn.rtype.rs2)
     val = badvaddr;
     break;
   case 3:
-    val = ebase;
+    val = evec;
     break;
   case 4:
     val = count;
@@ -22,6 +22,9 @@ switch(insn.rtype.rs2)
   case 5:
     val = compare;
     break;
+  case 6:
+    val = cause;
+    break;
 
   case 8:
     val = MEMSIZE >> 12;
diff --git a/riscv/insns/mtpcr.h b/riscv/insns/mtpcr.h
index bcc613a..1a31a32 100644
--- a/riscv/insns/mtpcr.h
+++ b/riscv/insns/mtpcr.h
@@ -9,7 +9,7 @@ switch(insn.rtype.rs2)
     epc = RS1;
     break;
   case 3:
-    ebase = RS1 & ~0xFFF;
+    evec = RS1;
     break;
   case 4:
     count = RS1;
diff --git a/riscv/mmu.h b/riscv/mmu.h
index 9bfbeac..1b8a422 100644
--- a/riscv/mmu.h
+++ b/riscv/mmu.h
@@ -50,9 +50,9 @@ private:
   {
     if(addr & (size-1))
     {
+      badvaddr = addr;
       if(fetch)
         throw trap_instruction_address_misaligned;
-      badvaddr = addr;
       throw trap_data_address_misaligned;
     }
   }
@@ -61,9 +61,9 @@ private:
   {
     if(addr >= memsz || addr + size > memsz)
     {
+      badvaddr = addr;
       if(fetch)
         throw trap_instruction_access_fault;
-      badvaddr = addr;
       throw store ? trap_store_access_fault : trap_load_access_fault;
     }
   }
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 271afbf..b018347 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -15,9 +15,10 @@ processor_t::processor_t(sim_t* _sim, char* _mem, size_t _memsz)
   memset(R,0,sizeof(R));
   memset(FR,0,sizeof(FR));
   pc = 0;
-  ebase = 0;
+  evec = 0;
   epc = 0;
   badvaddr = 0;
+  cause = 0;
   tid = 0;
   pcr_k0 = 0;
   pcr_k1 = 0;
@@ -109,8 +110,9 @@ void processor_t::take_trap(trap_t t, bool noisy)
            id, trap_name(t), (unsigned long long)pc);
 
   set_sr((((sr & ~SR_ET) | SR_S) & ~SR_PS) | ((sr & SR_S) ? SR_PS : 0));
+  cause = t;
   epc = pc;
-  pc = ebase + t*128;
+  pc = evec;
   badvaddr = mmu.get_badvaddr();
 }
 
diff --git a/riscv/processor.h b/riscv/processor.h
index fab6c9c..c1e4740 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -26,7 +26,8 @@ private:
   reg_t pc;
   reg_t epc;
   reg_t badvaddr;
-  reg_t ebase;
+  reg_t cause;
+  reg_t evec;
   reg_t tohost;
   reg_t fromhost;
   reg_t pcr_k0;