From: Luke Kenneth Casson Leighton Date: Tue, 27 Nov 2018 02:29:12 +0000 (+0000) Subject: split out cpu_mie into separate module X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a54966b8aca1fc5da8d3cb3a6ab1b7add4d9e146;p=rv32.git split out cpu_mie into separate module --- diff --git a/cpu.py b/cpu.py index 4b877f4..17172c9 100644 --- a/cpu.py +++ b/cpu.py @@ -79,26 +79,7 @@ class MIE: self.meie = Signal(name="mie_meie") self.mtie = Signal(name="mie_mtie") self.msie = Signal(name="mie_msie") - self.seie = Signal(name="mie_seie") - self.ueie = Signal(name="mie_ueie") - self.stie = Signal(name="mie_stie") - self.utie = Signal(name="mie_utie") - self.ssie = Signal(name="mie_ssie") - self.usie = Signal(name="mie_usie") - - for n in dir(self): - if n in ['make', 'comb', 'sync'] or n.startswith("_"): - continue - self.comb += getattr(self, n).eq(0x0) - - self.sync += self.meie.eq(0) - self.sync += self.mtie.eq(0) - self.sync += self.msie.eq(0) - - def make(self): - return Cat( self.usie, self.ssie, 0, self.msie, - self.utie, self.stie, 0, self.mtie, - self.ueie, self.seie, 0, self.meie, ) + self.mie = Signal(32) class MIP: @@ -425,7 +406,7 @@ class CPU(Module): ] # mie c[csr_mie ] = [ - csr_output_value.eq(mie.make()), + csr_output_value.eq(mie.mie), csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value, csr_written_value), mie.meie.eq(csr_written_value[11]), @@ -666,6 +647,14 @@ class CPU(Module): misa = Misa(self.comb, self.sync) mip = MIP(self.comb, self.sync) + mii = Instance("CPUMIE", name="cpu_mie", + o_mie = mie.mie, + i_meie = mie.meie, + i_mtie = mie.mtie, + i_msie = mie.msie) + + self.specials += mii + ms = Instance("CPUMStatus", name="cpu_mstatus", o_mstatus = mstatus.mstatus, i_mpie = mstatus.mpie, diff --git a/cpu_mie.py b/cpu_mie.py new file mode 100644 index 0000000..8345ba9 --- /dev/null +++ b/cpu_mie.py @@ -0,0 +1,77 @@ +""" +/* + * Copyright 2018 Jacob Lifshay + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + */ +`timescale 1ns / 1ps +`include "riscv.vh" +`include "cpu.vh" +""" + +import string +from migen import * +from migen.fhdl import verilog +from migen.fhdl.structure import _Operator + +from riscvdefs import * +from cpudefs import * + +class CPUMIE(Module): + def __init__(self): + Module.__init__(self) + self.meie = Signal(name="mie_meie", reset=0) + self.mtie = Signal(name="mie_mtie", reset=0) + self.msie = Signal(name="mie_msie", reset=0) + self.seie = Signal(name="mie_seie") + self.ueie = Signal(name="mie_ueie") + self.stie = Signal(name="mie_stie") + self.utie = Signal(name="mie_utie") + self.ssie = Signal(name="mie_ssie") + self.usie = Signal(name="mie_usie") + + for n in dir(self): + if n.startswith("_"): + continue + n = getattr(self, n) + if not isinstance(n, Signal): + continue + self.comb += n.eq(0x0) + + self.mie = Signal(32) + + self.sync += self.mie.eq(self.make()) + + def make(self): + return Cat( self.usie, self.ssie, 0, self.msie, + self.utie, self.stie, 0, self.mtie, + self.ueie, self.seie, 0, self.meie, ) + + + +if __name__ == "__main__": + example = CPUMIE() + print(verilog.convert(example, + { + example.meie, + example.mtie, + example.msie, + example.mie, + }))