From: lkcl Date: Sun, 16 Apr 2023 09:13:34 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls009_v1~49 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a785fcbc708bfa8d735edfdd954a165f4329ae05;p=libreriscv.git --- diff --git a/openpower/sv/remap.mdwn b/openpower/sv/remap.mdwn index 0eb80a6d2..938f80ee0 100644 --- a/openpower/sv/remap.mdwn +++ b/openpower/sv/remap.mdwn @@ -34,13 +34,15 @@ that for example a single FMAC may be used in a single hardware-controlled 100% Deterministic loop to perform 5x3 times 3x4 Matrix multiplication, generating 60 FMACs *without needing explicit assembler unrolling*. Additional uses include regular "Structure Packing" such as RGB pixel -data extraction and reforming. +data extraction and reforming (although less costly vec2/3/4 reshaping +is achievable with `PACK/UNPACK`). REMAP, like all of SV, is abstracted out, meaning that unlike traditional Vector ISAs which would typically only have a limited set of instructions that can be structure-packed (LD/ST and Move operations being the most common), REMAP may be applied to -literally any instruction: CRs, Arithmetic, Logical, LD/ST, anything. +literally any instruction: CRs, Arithmetic, Logical, LD/ST, even +Vectorised Branch-Conditional. When SUBVL is greater than 1 a given group of Subvector elements are kept together: effectively the group becomes the