From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 26 Nov 2018 06:26:40 +0000 (+0000)
Subject: add misa and mstatus csrs
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=aa88fdbeaa042eb10ff1b76baca2c59036cf9bf0;p=rv32.git

add misa and mstatus csrs
---

diff --git a/cpu.py b/cpu.py
index 3b7b802..b5f863c 100644
--- a/cpu.py
+++ b/cpu.py
@@ -292,11 +292,14 @@ class CSR:
 
         return Case(self.number, c)
 
-    def evaluate_csr_funct3_op(self, funct3, previous_value, written_value):
-        c = { "default": Constant(0, 32)}
-        for f in [F3.csrrw, F3.csrrwi]: c[f] = written_value
-        for f in [F3.csrrs, F3.csrrsi]: c[f] = written_value | previous_value
-        for f in [F3.csrrc, F3.csrrci]: c[f] = ~written_value & previous_value
+    def evaluate_csr_funct3_op(self, funct3, previous, written):
+        c = { "default": written.eq(Constant(0, 32))}
+        for f in [F3.csrrw, F3.csrrwi]:
+            c[f] = written.eq(self.input_value)
+        for f in [F3.csrrs, F3.csrrsi]:
+            c[f] = written.eq(self.input_value | previous)
+        for f in [F3.csrrc, F3.csrrci]:
+            c[f] = written.eq(~self.input_value & previous)
         return Case(funct3, c)
 
 
@@ -397,7 +400,7 @@ class CPU(Module):
         s.append(i)
         return s
 
-    def main_block(self, minfo, csr, mi, m, mstatus, ft, dc,
+    def main_block(self, minfo, misa, csr, mi, m, mstatus, ft, dc,
                          load_store_misaligned,
                          loaded_value, alu_result,
                          lui_auipc_result):
@@ -405,14 +408,14 @@ class CPU(Module):
         c[FOS.empty] = []
         c[FOS.trap] = self.handle_trap(m, mstatus, ft, dc,
                                        load_store_misaligned)
-        c[FOS.valid] = self.handle_valid(minfo, csr, mi, m, mstatus, ft, dc,
+        c[FOS.valid] = self.handle_valid(minfo, misa, csr, mi, m, mstatus, ft, dc,
                                        load_store_misaligned,
                                        loaded_value,
                                        alu_result,
                                        lui_auipc_result)
         return Case(ft.output_state, c)
 
-    def handle_valid(self, minfo, csr, mi, m, mstatus, ft, dc,
+    def handle_valid(self, minfo, misa, csr, mi, m, mstatus, ft, dc,
                            load_store_misaligned,
                            loaded_value, alu_result,
                            lui_auipc_result):
@@ -445,7 +448,7 @@ class CPU(Module):
               )
 
         i = i.Elif((dc.act & DA.csr) != 0,
-                self.handle_csr(minfo, mstatus, dc, csr)
+                self.handle_csr(minfo, misa, mstatus, dc, csr)
               )
 
         # fence, store, branch
@@ -456,9 +459,9 @@ class CPU(Module):
 
         return i
 
-    def handle_csr(self, minfo, mstatus, dc, csr):
-        csr_output_value = Signal()
-        csr_written_value = Signal()
+    def handle_csr(self, minfo, misa, mstatus, dc, csr):
+        csr_output_value = Signal(32)
+        csr_written_value = Signal(32)
         c = {}
 
         # cycle
@@ -475,36 +478,23 @@ class CPU(Module):
         c[csr_marchid  ] = csr_output_value.eq(minfo.marchid  )
         c[csr_mimpid   ] = csr_output_value.eq(minfo.mimpid   )
         c[csr_mhartid  ] = csr_output_value.eq(minfo.mhartid  )
-
-        return Case(csr.number, c)
+        # misa
+        c[csr_misa     ] = csr_output_value.eq(misa.misa)
+        # mstatus
+        c[csr_mstatus  ] = [
+            csr_output_value.eq(mstatus.make()),
+            csr.evaluate_csr_funct3_op(dc.funct3, csr_written_value,
+                                                  csr_output_value),
+            mstatus.mpie.eq(csr_written_value[7]),
+            mstatus.mie.eq(csr_written_value[3])
+        ]
+
+        return [Case(csr.number, c),
+                If(csr.reads,
+                    self.write_register(dc.rd, csr_output_value)
+                )]
 
         """
-                `csr_misa: begin
-                    csr_output_value = misa;
-                end
-                `csr_mstatus: begin
-                    csr_output_value = make_mstatus(mstatus_tsr,
-                                                    mstatus_tw,
-                                                    mstatus_tvm,
-                                                    mstatus_mxr,
-                                                    mstatus_sum,
-                                                    mstatus_mprv,
-                                                    mstatus_xs,
-                                                    mstatus_fs,
-                                                    mstatus_mpp,
-                                                    mstatus_spp,
-                                                    mstatus_mpie,
-                                                    mstatus_spie,
-                                                    mstatus_upie,
-                                                    mstatus_mie,
-                                                    mstatus_sie,
-                                                    mstatus_uie);
-                    csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
-                    if(csr_writes) begin
-                        mstatus_mpie = csr_written_value[7];
-                        mstatus_mie = csr_written_value[3];
-                    end
-                end
                 `csr_mie: begin
                     csr_output_value = 0;
                     csr_output_value[11] = mie_meie;
@@ -771,7 +761,7 @@ class CPU(Module):
 
         misaligned_jump_target = Signal()
         self.comb += misaligned_jump_target.eq(ft.target_pc[1])
-
+ 
         branch_arg_a = Signal(32)
         branch_arg_b = Signal(32)
         self.comb += branch_arg_a.eq(Cat( register_rs1[0:31],
@@ -801,7 +791,8 @@ class CPU(Module):
         minfo = MInfo(self.comb)
 
         self.sync += If(~self.reset,
-                        self.main_block(minfo, csr, mi, m, mstatus, ft, dc,
+                        self.main_block(minfo, misa, csr, mi, m,
+                                        mstatus, ft, dc,
                                         load_store_misaligned,
                                         loaded_value,
                                        alu_result,