From: Tim Newsome Date: Fri, 22 Apr 2016 22:08:35 +0000 (-0700) Subject: Add debug rom code. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ae566cba20a70f92c6cb778068e6e523602a2756;p=riscv-isa-sim.git Add debug rom code. --- diff --git a/debug_rom/Makefile b/debug_rom/Makefile new file mode 100644 index 0000000..a6da5a8 --- /dev/null +++ b/debug_rom/Makefile @@ -0,0 +1,17 @@ +# Recursive make is bad, but in this case we're cross compiling which is a +# pretty unusual use case. + +CC = $(RISCV)/bin/riscv64-unknown-elf-gcc +OBJCOPY = $(RISCV)/bin/riscv64-unknown-elf-objcopy + +%.o: %.S + $(CC) -c $< + +debug_rom: debug_rom.o + $(CC) -nostdlib -nostartfiles -Tlink.ld -o $@ $^ + +debug_rom.raw: debug_rom + $(OBJCOPY) -O binary --only-section .text debug_rom debug_rom.raw + +clean: + rm -f debug_rom debug_rom.o debug_rom.raw diff --git a/debug_rom/debug_rom.S b/debug_rom/debug_rom.S new file mode 100755 index 0000000..230f4b4 --- /dev/null +++ b/debug_rom/debug_rom.S @@ -0,0 +1,105 @@ +# This code should be functional. Doesn't have to be optimal. +# I'm writing it to prove that it can be done. + +# TODO: Update these constants once they're finalized in the doc. + +#define DCSR 0x790 +#define DCSR_CAUSE_DEBINT 3 +#define DCSR_HALT_OFFSET 3 +#define DCSR_DEBUGINT_OFFSET 10 + +#define DSCRATCH 0x792 + +#define MCPUID 0xf00 +#define MHARTID 0xf10 + +#define DEBUG_RAM 0x400 +#define DEBUG_RAM_SIZE 64 + +#define SETHALTNOT 0x100 +#define CLEARHALTNOT 0x104 +#define CLEARDEBINT 0x108 + + .global entry + .global resume + + # Automatically called when Debug Mode is first entered. +entry: j _entry + # Should be called by Debug RAM code that has finished execution and + # wants to return to Debug Mode. +resume: + # Clear debug interrupt. +clear_debint: + csrr s1, MHARTID + sw s1, CLEARDEBINT(zero) +clear_debint_loop: + csrr s1, DCSR + andi s1, s1, (1<