From: Luke Kenneth Casson Leighton Date: Sat, 28 Jul 2018 09:16:14 +0000 (+0100) Subject: fix PADDR to 32 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=af8810bec6f97da3608254a024f29fcb2a458457;p=pinmux.git fix PADDR to 32 --- diff --git a/src/bsv/bsv_lib/slow_peripherals_template.bsv b/src/bsv/bsv_lib/slow_peripherals_template.bsv index 2f4a828..9c992fe 100644 --- a/src/bsv/bsv_lib/slow_peripherals_template.bsv +++ b/src/bsv/bsv_lib/slow_peripherals_template.bsv @@ -41,7 +41,7 @@ package slow_peripherals; `endif endinterface interface Ifc_slow_peripherals; - interface AXI4_Slave_IFC#(`ADDR,`DATA,`USERSPACE) axi_slave; + interface AXI4_Slave_IFC#(`PADDR,`DATA,`USERSPACE) axi_slave; interface SP_dedicated_ios slow_ios; `ifdef CLINT method Bit#(1) msip_int; @@ -83,7 +83,7 @@ package slow_peripherals; /*=======================================================*/ - AXI4_Lite_Fabric_IFC #(1, Num_Slow_Slaves, `ADDR, `DATA,`USERSPACE) + AXI4_Lite_Fabric_IFC #(1, Num_Slow_Slaves, `PADDR, `DATA,`USERSPACE) slow_fabric <- mkAXI4_Lite_Fabric(fn_slow_address_mapping); Ifc_AXI4Lite_AXI4_Bridge bridge<-mkAXI4Lite_AXI4_Bridge(fast_clock,fast_reset); diff --git a/src/bsv/bsv_lib/slow_tuple2_template.bsv b/src/bsv/bsv_lib/slow_tuple2_template.bsv index ce5989b..dbde384 100644 --- a/src/bsv/bsv_lib/slow_tuple2_template.bsv +++ b/src/bsv/bsv_lib/slow_tuple2_template.bsv @@ -11,7 +11,7 @@ package slow_memory_map; /* ==== define the number of slow peripheral irqs ==== */ function Tuple2#(Bool, Bit#(TLog#(Num_Slow_Slaves))) - fn_slow_address_mapping (Bit#(`ADDR) addr); + fn_slow_address_mapping (Bit#(`PADDR) addr); `ifdef CLINT if(addr>=`ClintBase && addr<=`ClintEnd) return tuple2(True,fromInteger(valueOf(CLINT_slave_num))); diff --git a/src/bsv/bsv_lib/soc_template.bsv b/src/bsv/bsv_lib/soc_template.bsv index 166ba81..65e1dce 100644 --- a/src/bsv/bsv_lib/soc_template.bsv +++ b/src/bsv/bsv_lib/soc_template.bsv @@ -96,7 +96,7 @@ package socgen; `endif `ifdef DDR (*prefix="M_AXI"*) interface - AXI4_Master_IFC#(`ADDR, `DATA, `USERSPACE) master; + AXI4_Master_IFC#(`PADDR, `DATA, `USERSPACE) master; `endif `ifdef HYPER (*always_ready,always_enabled*) @@ -152,7 +152,7 @@ package socgen; // Fabric AXI4_Fabric_IFC #(Num_Masters, Num_Fast_Slaves, - `ADDR, `DATA,`USERSPACE) + `PADDR, `DATA,`USERSPACE) fabric <- mkAXI4_Fabric(fn_addr_to_slave_num); // Connect traffic generators to fabric diff --git a/src/bsv/peripheral_gen/flexbus.py b/src/bsv/peripheral_gen/flexbus.py index 7302d46..074e843 100644 --- a/src/bsv/peripheral_gen/flexbus.py +++ b/src/bsv/peripheral_gen/flexbus.py @@ -18,7 +18,7 @@ class flexbus(PBase): def mkfast_peripheral(self): return "AXI4_Slave_to_FlexBus_Master_Xactor_IFC " + \ - "#(`ADDR, `DATA, `USERSPACE)\n" + \ + "#(`PADDR, `DATA, `USERSPACE)\n" + \ " fb{0} <- mkAXI4_Slave_to_FlexBus_Master_Xactor;" def _mk_connection(self, name=None, count=0): diff --git a/src/bsv/pinmux_generator.py b/src/bsv/pinmux_generator.py index 1589468..36d6e4e 100644 --- a/src/bsv/pinmux_generator.py +++ b/src/bsv/pinmux_generator.py @@ -443,7 +443,7 @@ def write_instances(idef, p, ifaces): with open(idef, 'w') as bsv_file: txt = '''\ `define ADDR {0} -`define PADDR {0} +`define PADDR 32 `define DATA {1} `define Reg_width {1} `define USERSPACE 0