From: Luke Kenneth Casson Leighton Date: Sun, 30 Jan 2022 22:03:24 +0000 (+0000) Subject: create Memory for Cache Tags in I-Cache X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b2413227cf6e4de82f691352e163f009fc31efbc;p=soc.git create Memory for Cache Tags in I-Cache another huge reduction in number of LUT4s, uses (again) a combinatorial-read sync-write --- diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py index e594bf8a..71b3f989 100644 --- a/src/soc/experiment/icache.py +++ b/src/soc/experiment/icache.py @@ -261,7 +261,7 @@ def get_tag(addr): # Read a tag from a tag memory row def read_tag(way, tagset): - return tagset.word_select(way, TAG_WIDTH)[:TAG_BITS] + return tagset.word_select(way, TAG_BITS) # Write a tag to tag memory row def write_tag(way, tagset, tag): @@ -477,11 +477,12 @@ class ICache(FetchUnitInterface, Elaboratable): # Cache hit detection, output to fetch2 and other misc logic def icache_comb(self, m, use_previous, r, req_index, req_row, req_hit_way, req_tag, real_addr, req_laddr, - cache_tags, cache_valids, access_ok, + cache_valids, access_ok, req_is_hit, req_is_miss, replace_way, plru_victim, cache_out_row): comb = m.d.comb + m.submodules.rd_tag = rd_tag = self.tagmem.read_port(domain="comb") i_in, i_out, bus = self.i_in, self.i_out, self.bus flush_in, stall_out = self.flush_in, self.stall_out @@ -517,7 +518,8 @@ class ICache(FetchUnitInterface, Elaboratable): # i_in.req asserts Decoder active cvb = Signal(NUM_WAYS) ctag = Signal(TAG_RAM_WIDTH) - comb += ctag.eq(cache_tags[req_index]) + comb += rd_tag.addr.eq(req_index) + comb += ctag.eq(rd_tag.data) comb += cvb.eq(cache_valids[req_index]) m.submodules.store_way_e = se = Decoder(NUM_WAYS) comb += se.i.eq(r.store_way) @@ -646,9 +648,11 @@ class ICache(FetchUnitInterface, Elaboratable): def icache_miss_clr_tag(self, m, r, replace_way, req_index, - cache_tags, cache_valids): + cache_valids): comb = m.d.comb sync = m.d.sync + m.submodules.wr_tag = wr_tag = self.tagmem.write_port( + granularity=TAG_BITS) # Get victim way from plru sync += r.store_way.eq(replace_way) @@ -659,12 +663,13 @@ class ICache(FetchUnitInterface, Elaboratable): comb += cv.bit_select(replace_way, 1).eq(0) sync += cache_valids[req_index].eq(cv) - for i in range(NUM_WAYS): - with m.If(i == replace_way): - tagset = Signal(TAG_RAM_WIDTH) - comb += tagset.eq(cache_tags[r.store_index]) - comb += write_tag(i, tagset, r.store_tag) - sync += cache_tags[r.store_index].eq(tagset) + # use write-port "granularity" to select the tag to write to + # TODO: the Memory should be multipled-up (by NUM_TAGS) + tagset = Signal(TAG_RAM_WIDTH) + comb += tagset.eq(r.store_tag << (replace_way*TAG_BITS)) + comb += wr_tag.en.eq(1<