From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 25 Aug 2019 11:38:34 +0000 (+0100)
Subject: code comments
X-Git-Tag: ls180-24jan2020~382
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b411294b2bf19bf387c8f45812f4216a1a71d7a5;p=ieee754fpu.git

code comments
---

diff --git a/src/ieee754/fpmul/mul0.py b/src/ieee754/fpmul/mul0.py
index 6b00762a..7f19fcfc 100644
--- a/src/ieee754/fpmul/mul0.py
+++ b/src/ieee754/fpmul/mul0.py
@@ -41,6 +41,7 @@ class FPMulStage0Mod(PipeModBase):
                      self.o.z.s.eq(self.i.a.s ^ self.i.b.s)
         ]
 
+        # pass through context
         comb += self.o.oz.eq(self.i.oz)
         comb += self.o.out_do_z.eq(self.i.out_do_z)
         comb += self.o.ctx.eq(self.i.ctx)
diff --git a/src/ieee754/fpmul/mul1.py b/src/ieee754/fpmul/mul1.py
index ebae4fd5..45826b79 100644
--- a/src/ieee754/fpmul/mul1.py
+++ b/src/ieee754/fpmul/mul1.py
@@ -29,8 +29,9 @@ class FPMulStage1Mod(PipeModBase):
         m = Module()
         comb = m.d.comb
 
-        # copy sign
+        # copy sign as-is
         comb += self.o.z.s.eq(self.i.z.s)
+
         # results are in the range 0.25 to 0.999999999999
         # sometimes the MSB will be zero, (0.5 * 0.5 = 0.25 which
         # in binary is 0b010000) so to compensate for that we have
@@ -53,6 +54,7 @@ class FPMulStage1Mod(PipeModBase):
             self.o.of.sticky.eq(p[0:mw].bool()) # sticky
         ]
 
+        # pass through context
         comb += self.o.out_do_z.eq(self.i.out_do_z)
         comb += self.o.oz.eq(self.i.oz)
         comb += self.o.ctx.eq(self.i.ctx)