From: Tim Newsome <tim@sifive.com>
Date: Mon, 19 Mar 2018 16:35:55 +0000 (-0700)
Subject: Merge pull request #182 from riscv/reset_bits
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b4997aa4be6ab17b7a838b53e1ddea32726dad66;hp=b4997aa4be6ab17b7a838b53e1ddea32726dad66;p=riscv-isa-sim.git

Merge pull request #182 from riscv/reset_bits

Implement debug havereset bits
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