From: Henry Styles Date: Wed, 9 Aug 2017 17:45:16 +0000 (-0700) Subject: Wip X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b83e9747282019746d1add650d07337b286719f6;p=sifive-blocks.git Wip --- diff --git a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala index 6776b2e..7288461 100644 --- a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala +++ b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala @@ -22,7 +22,7 @@ class XilinxVC707MIG(c : XilinxVC707MIGParams)(implicit p: Parameters) extends L require((c.depthGB == 1) || (c.depthGB == 4)) // Suppoted address map configuratons - val address = if(c.depthGB == 1) Seq(AddressSet(0x80000000L , 0x80000000L-1)) //2GB @ 2GB + val address = if(c.depthGB == 1) Seq(AddressSet(0x80000000L , 0x40000000L-1)) //1GB @ 2GB else Seq(AddressSet(0x80000000L, 0x80000000L-1), //2GB @ 2GB AddressSet(0x2080000000L, 0x80000000L-1)) //2GB @ 130GB