From: Michael Nolan <mtnolan2640@gmail.com>
Date: Thu, 7 May 2020 18:18:32 +0000 (-0400)
Subject: Get test_cmp working
X-Git-Tag: div_pipeline~1356
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bbb0f41ab180fbab1427b320f91d795dac84d70c;p=soc.git

Get test_cmp working
---

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index a5712320..8a244a3e 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -2,7 +2,7 @@ from functools import wraps
 from soc.decoder.orderedset import OrderedSet
 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
                                         selectconcat)
-from soc.decoder.power_enums import spr_dict
+from soc.decoder.power_enums import spr_dict, XER_bits
 from soc.decoder.helpers import exts
 from collections import namedtuple
 import math
@@ -15,7 +15,7 @@ special_sprs = {
     'LR': 8,
     'CTR': 9,
     'TAR': 815,
-    'XER': 0,
+    'XER': 1,
     'VRSAVE': 256}
 
 
@@ -200,6 +200,7 @@ class ISACaller:
                           'undefined': self.undefined,
                           'mode_is_64bit': True,
                           }
+        self.namespace.update(XER_bits)
 
         # field-selectable versions of Condition Register TODO check bitranges?
         self.crl = []
@@ -228,7 +229,12 @@ class ISACaller:
             else:
                 sig = getattr(fields, name)
             val = yield sig
-            self.namespace[name] = SelectableInt(val, sig.width)
+            if name == 'BF':
+                self.namespace[name] = val
+            else:
+                self.namespace[name] = SelectableInt(val, sig.width)
+
+        self.namespace['XER'] = self.spr['XER']
 
     def handle_carry(self, inputs, outputs):
         inv_a = yield self.dec2.invert_a
diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py
index 1c7cb9a0..6e3ccdd2 100644
--- a/src/soc/decoder/isa/test_caller.py
+++ b/src/soc/decoder/isa/test_caller.py
@@ -138,7 +138,6 @@ class DecoderTestCase(FHDLTestCase):
             # Verified with QEMU
             self.assertEqual(sim.gpr(3), SelectableInt(0x80000000, 64))
 
-    @unittest.skip("broken (XER)")
     def test_cmp(self):
         lst = ["addis 1, 0, 0xffff",
                "addis 2, 0, 0xffff",
diff --git a/src/soc/decoder/power_enums.py b/src/soc/decoder/power_enums.py
index ef919ee1..ca17eef4 100644
--- a/src/soc/decoder/power_enums.py
+++ b/src/soc/decoder/power_enums.py
@@ -229,3 +229,12 @@ for row in spr_csv:
     spr_dict[int(row['Idx'])] = info
 fields = [(row['SPR'], int(row['Idx'])) for row in spr_csv]
 SPR = Enum('SPR', fields)
+
+
+XER_bits = {
+    'SO': 32,
+    'OV': 33,
+    'CA': 34,
+    'OV32': 44,
+    'CA32': 45
+    }