From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 13 Jul 2020 18:07:08 +0000 (+0100)
Subject: add mtmsrd instruction and unit test
X-Git-Tag: div_pipeline~56
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bd2acc23a6b1e4b2cb02bbdbf6f6ed776eb27ed9;p=soc.git

add mtmsrd instruction and unit test
---

diff --git a/libreriscv b/libreriscv
index a0ed154f..12e9237b 160000
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit a0ed154f4604d296ffc77e0489c4c0f2e23c94dc
+Subproject commit 12e9237b896ad233cb18946b34dab17d976f415c
diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index 769ae863..2444d7d5 100644
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -175,8 +175,13 @@ class TrapMainStage(PipeModBase):
                 with m.Else():
                     # Architecture says to leave out bits 3 (HV), 51 (ME)
                     # and 63 (LE) (IBM bit numbering)
-                    for stt, end in [(1,12), (13, 60), (61, 64)]:
-                        comb += msr_o.data[stt:end].eq(a_i[stt:end])
+                    with m.If(op.insn_type == MicrOp.OP_MTMSRD):
+                        for stt, end in [(1,12), (13, 60), (61, 64)]:
+                            comb += msr_o.data[stt:end].eq(a_i[stt:end])
+                    with m.Else():
+                        # mtmsr - 32-bit, only room for bottom 32 LSB flags
+                        for stt, end in [(1,12), (13, 32)]:
+                            comb += msr_o.data[stt:end].eq(a_i[stt:end])
                     msr_check_pr(m, msr_o.data)
                 comb += msr_o.ok.eq(1)
 
diff --git a/src/soc/fu/trap/test/test_pipe_caller.py b/src/soc/fu/trap/test/test_pipe_caller.py
index 44fbba6a..279bac26 100644
--- a/src/soc/fu/trap/test/test_pipe_caller.py
+++ b/src/soc/fu/trap/test/test_pipe_caller.py
@@ -120,10 +120,23 @@ class TrapTestCase(FHDLTestCase):
         initial_regs[1] = 0xffffffffffffffff
         self.run_tst_program(Program(lst, bigendian), initial_regs)
 
+    def test_4_mtmsrd_0(self):
+        lst = ["mtmsrd 1,0"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0xffffffffffffffff
+        self.run_tst_program(Program(lst, bigendian), initial_regs)
+
+    def test_5_mtmsrd_1(self):
+        lst = ["mtmsrd 1,1"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0xffffffffffffffff
+        self.run_tst_program(Program(lst, bigendian), initial_regs)
+
     def test_999_illegal(self):
         # ok, um this is a bit of a cheat: use an instruction we know
         # is not implemented by either ISACaller or the core
-        lst = ["tbegin."]
+        lst = ["tbegin.",
+               "mtmsr 1,1"] # should not get executed
         initial_regs = [0] * 32
         self.run_tst_program(Program(lst, bigendian), initial_regs)