From: Megan Wachs <megan@sifive.com>
Date: Thu, 8 Jun 2017 23:25:20 +0000 (-0700)
Subject: GPIO: Make GPIO peripheral another listable one
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c89f163c0d045f454f8b0f813aa19047025e7dca;p=sifive-blocks.git

GPIO: Make GPIO peripheral another listable one
---

diff --git a/src/main/scala/devices/gpio/GPIOPeriphery.scala b/src/main/scala/devices/gpio/GPIOPeriphery.scala
index 20f8b5d..3c7a2ec 100644
--- a/src/main/scala/devices/gpio/GPIOPeriphery.scala
+++ b/src/main/scala/devices/gpio/GPIOPeriphery.scala
@@ -11,22 +11,27 @@ import rocketchip.{
 }
 import uncore.tilelink2.TLFragmenter
 
-case object PeripheryGPIOKey extends Field[GPIOParams]
+case object PeripheryGPIOKey extends Field[Seq[GPIOParams]]
 
 trait HasPeripheryGPIO extends HasTopLevelNetworks {
   val gpioParams = p(PeripheryGPIOKey)
-  val gpio = LazyModule(new TLGPIO(peripheryBusBytes, gpioParams))
-  gpio.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
-  intBus.intnode := gpio.intnode
+  val gpio = gpioParams map {params =>
+    val gpio = LazyModule(new TLGPIO(peripheryBusBytes, params))
+    gpio.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
+    intBus.intnode := gpio.intnode
+    gpio
+  }
 }
 
 trait HasPeripheryGPIOBundle extends HasTopLevelNetworksBundle {
   val outer: HasPeripheryGPIO
-  val gpio = new GPIOPortIO(outer.gpioParams)
+  val gpio = HeterogeneousBag(outer.gpioParams(map(new GPIOPortIO(_))))
 }
 
 trait HasPeripheryGPIOModule extends HasTopLevelNetworksModule {
   val outer: HasPeripheryGPIO
   val io: HasPeripheryGPIOBundle
-  io.gpio <> outer.gpio.module.io.port
+  (io.gpio zip outer.gpio) foreach { case (io, device) =>
+    io.gpio <> device.module.io.port
+  }
 }