From: Jacob Lifshay Date: Tue, 6 Oct 2020 00:16:29 +0000 (-0700) Subject: print regs in hex X-Git-Tag: 24jan2021_ls180~225 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c926aac9eeca02587d3c44d666adf5b6e1315090;p=soc.git print regs in hex --- diff --git a/src/soc/fu/div/test/helper.py b/src/soc/fu/div/test/helper.py index 3b57b529..f368cf74 100644 --- a/src/soc/fu/div/test/helper.py +++ b/src/soc/fu/div/test/helper.py @@ -178,8 +178,7 @@ class DivTestHelper(unittest.TestCase): except AttributeError: pass msg = "%s: %s" % (div_pipe_kind.name, code) - msg += " %s" % (repr(prog.assembly)) - msg += " %s" % (repr(test.regs)) + msg += f" {prog.assembly!r} {list(map(hex, test.regs))!r}" yield from self.check_alu_outputs(alu, pdecode2, isa_sim, msg, pia_res)