From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 15 Jul 2020 13:21:23 +0000 (+0100)
Subject: use case statement in PowerDecode2
X-Git-Tag: div_pipeline~29
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c9ae3ffaf2cd01599b254f60f9c8b47c6f2ed5d8;p=soc.git

use case statement in PowerDecode2
---

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index 06bdf14e..3f5686ba 100644
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -368,15 +368,14 @@ class DecodeOut2(Elaboratable):
         # B, BC or BCREG: potential implicit register (LR) output
         # these give bl, bcl, bclrl, etc.
         op = self.dec.op
-        with m.If((op.internal_op == MicrOp.OP_BC) |
-                  (op.internal_op == MicrOp.OP_B) |
-                  (op.internal_op == MicrOp.OP_BCREG)):
-            with m.If(self.lk): # "link" mode
-                comb += self.fast_out.data.eq(FastRegs.LR) # constant: LR
-                comb += self.fast_out.ok.eq(1)
+        with m.Switch(op.internal_op):
+            with m.Case(MicrOp.OP_BC, MicrOp.OP_B, MicrOp.OP_BCREG):
+                with m.If(self.lk): # "link" mode
+                    comb += self.fast_out.data.eq(FastRegs.LR) # constant: LR
+                    comb += self.fast_out.ok.eq(1)
 
-        # RFID 2nd spr (fast)
-        with m.If(op.internal_op == MicrOp.OP_RFID):
+            # RFID 2nd spr (fast)
+            with m.Case(MicrOp.OP_RFID):
                 comb += self.fast_out.data.eq(FastRegs.SRR1) # constant: SRR1
                 comb += self.fast_out.ok.eq(1)