From: Andrew Waterman <waterman@eecs.berkeley.edu>
Date: Sat, 1 Feb 2014 02:10:35 +0000 (-0800)
Subject: Add rv32si tests, including illegality of shamt[5]
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cdd27919a7314324aece473270364e358c89f54f;p=riscv-tests.git

Add rv32si tests, including illegality of shamt[5]
---

diff --git a/env b/env
index 217bb5e..d4959de 160000
--- a/env
+++ b/env
@@ -1 +1 @@
-Subproject commit 217bb5eef46deb0eeac7b8f11c9d36d9310feabb
+Subproject commit d4959de3364556560c51cda343d04629a0d1cd1f
diff --git a/isa/Makefile b/isa/Makefile
index 1009c27..53c11ad 100644
--- a/isa/Makefile
+++ b/isa/Makefile
@@ -10,6 +10,7 @@ include $(isa_src_dir)/rv64uv/Makefrag
 include $(isa_src_dir)/rv64si/Makefrag
 include $(isa_src_dir)/rv64sv/Makefrag
 include $(isa_src_dir)/rv32ui/Makefrag
+include $(isa_src_dir)/rv32si/Makefrag
 
 default: all
 
@@ -69,6 +70,7 @@ tests += $$($(1)_v_vec_tests)
 endef
 
 $(eval $(call compile_template,rv32ui,-m32))
+$(eval $(call compile_template,rv32si,-m32))
 $(eval $(call compile_template,rv64ui))
 $(eval $(call compile_template,rv64uf))
 $(eval $(call compile_template,rv64uv))
diff --git a/isa/rv32si/Makefrag b/isa/rv32si/Makefrag
new file mode 100644
index 0000000..7ffc060
--- /dev/null
+++ b/isa/rv32si/Makefrag
@@ -0,0 +1,15 @@
+#=======================================================================
+# Makefrag for rv32si tests
+#-----------------------------------------------------------------------
+
+rv32si_sc_tests = \
+	csr \
+	shamt \
+
+rv32si_mc_tests = \
+	ipi \
+
+rv32si_p_tests = $(addprefix rv32si-p-, $(rv32si_sc_tests))
+rv32si_pm_tests = $(addprefix rv32si-pm-, $(rv32si_mc_tests))
+
+spike_tests += $(rv32si_p_tests) $(rv32si_pm_tests)
diff --git a/isa/rv32si/csr.S b/isa/rv32si/csr.S
new file mode 100644
index 0000000..c229b50
--- /dev/null
+++ b/isa/rv32si/csr.S
@@ -0,0 +1,14 @@
+#*****************************************************************************
+# csr.S
+#-----------------------------------------------------------------------------
+#
+# Test CSRRx and CSRRxI instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV32S
+
+#include "../rv64si/csr.S"
diff --git a/isa/rv32si/ipi.S b/isa/rv32si/ipi.S
new file mode 100644
index 0000000..4682bee
--- /dev/null
+++ b/isa/rv32si/ipi.S
@@ -0,0 +1,14 @@
+#*****************************************************************************
+# ipi.S
+#-----------------------------------------------------------------------------
+#
+# Test interprocessor interrupts.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV32S
+
+#include "../rv64si/ipi.S"
diff --git a/isa/rv32si/shamt.S b/isa/rv32si/shamt.S
new file mode 100644
index 0000000..df97287
--- /dev/null
+++ b/isa/rv32si/shamt.S
@@ -0,0 +1,44 @@
+#*****************************************************************************
+# csr.S
+#-----------------------------------------------------------------------------
+#
+# Test CSRRx and CSRRxI instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32S
+RVTEST_CODE_BEGIN
+
+  la t0, evec
+  csrw evec, t0
+
+  # Make sure slli with shamt[4] set is legal.
+  TEST_CASE( 2, a0, 65536, li a0, 1; slli a0, a0, 16);
+
+  # Make sure slli with shamt[4] set is not legal.
+  TEST_CASE( 3, x0, 1, slli a0, a0, 32);
+
+  TEST_PASSFAIL
+
+evec:
+  # Trapping on test 3 is good.
+  # Note that since the test didn't complete, TESTNUM is smaller by 1.
+  li t0, 2
+  bne TESTNUM, t0, fail
+
+  # Make sure CAUSE indicates an illegal instructino.
+  csrr t0, cause
+  li t1, CAUSE_ILLEGAL_INSTRUCTION
+  bne t0, t1, fail
+  j pass
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv32ui/srli.S b/isa/rv32ui/srli.S
index 61e01fb..a8ae06d 100644
--- a/isa/rv32ui/srli.S
+++ b/isa/rv32ui/srli.S
@@ -33,15 +33,6 @@ RVTEST_CODE_BEGIN
   TEST_IMM_OP( 15, srli, 0x00008484, 0x21212121, 14 );
   TEST_IMM_OP( 16, srli, 0x00000000, 0x21212121, 31 );
 
-  # Verify that shifts only use bottom five bits
-
-  TEST_IMM_OP( 17, srli, 0x21212121, 0x21212121, 0xffffffc0 );
-  TEST_IMM_OP( 18, srli, 0x10909090, 0x21212121, 0xffffffc1 );
-  TEST_IMM_OP( 19, srli, 0x00424242, 0x21212121, 0xffffffc7 );
-  TEST_IMM_OP( 20, srli, 0x00008484, 0x21212121, 0xffffffce );
-
-
-
   #-------------------------------------------------------------
   # Source/Destination tests
   #-------------------------------------------------------------
diff --git a/isa/rv64si/csr.S b/isa/rv64si/csr.S
index 846a483..389280d 100644
--- a/isa/rv64si/csr.S
+++ b/isa/rv64si/csr.S
@@ -44,7 +44,7 @@ RVTEST_CODE_BEGIN
 
 evec:
   # Trapping on tests 10, 11, and 13 is usually good news.
-  # Note that since the test didn't finished, TESTNUM is smaller by 1.
+  # Note that since the test didn't complete, TESTNUM is smaller by 1.
   li t0, 9
   beq TESTNUM, t0, privileged
   li t0, 10