From: Xan Date: Wed, 25 Apr 2018 04:54:50 +0000 (+0100) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~5562 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d09ae51ed1fb49e363e18d7cdea168596f89a5bc;p=libreriscv.git --- diff --git a/Harmonised_RVV/Packed_SIMD.mdwn b/Harmonised_RVV/Packed_SIMD.mdwn index e6043d642..03d61dfa4 100644 --- a/Harmonised_RVV/Packed_SIMD.mdwn +++ b/Harmonised_RVV/Packed_SIMD.mdwn @@ -7,7 +7,7 @@ RVP implementations may choose to load/store to/from Integer register file (rather than from a dedicated Vector register file). * VLD and VST in this case will have similar behaviour to LW/LD and SW/SD respectively, but only operate on up to VL elements (see point #4 below). -* Mapping of v0-31 <-> r0-31 *is fixed* at 1:1. (An exception may be made to map v1 to r5, as otherwise may clash with procedure linkage). +* Mapping of v0-31 <-> r0-31 **is fixed** at 1:1. (An exception may be made to map v1 to r5, as otherwise may clash with procedure linkage). * Thus, RVP implementations have a choice of providing a dedicated Vector register file, or sharing the integer register file, but not both simultaneously. (Supporting both would need a CSR mode switch bit). * If integer register file is used for vector operations, any callee saved registers (r2-4, 8-9, 18-27) must be saved with RVI SW or SD instructions, before being used as vector registers (this register saving behaviour is harmless but redundant when RVP code is run on a machine with a dedicated vector reg file).