From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 23 Jul 2019 09:29:37 +0000 (+0100)
Subject: reduce n_comb_stages for fpdiv first setup
X-Git-Tag: ls180-24jan2020~757
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d16a7e67fc94218a93b6042817f52493e13afdd2;p=ieee754fpu.git

reduce n_comb_stages for fpdiv first setup
---

diff --git a/src/ieee754/fpdiv/pipeline.py b/src/ieee754/fpdiv/pipeline.py
index 553af107..82a33e2c 100644
--- a/src/ieee754/fpdiv/pipeline.py
+++ b/src/ieee754/fpdiv/pipeline.py
@@ -87,15 +87,17 @@ class FPDIVBasePipe(ControlBase):
 
         # get number of stages, set up loop.
         n_stages = pspec.core_config.n_stages
-        n_comb_stages = self.pspec.n_comb_stages
+        max_n_comb_stages = self.pspec.n_comb_stages
         print ("n_stages", n_stages)
         stage_idx = 0
 
         end = False
         while not end:
 
+            n_comb_stages = max_n_comb_stages
             # needs to convert input from pipestart ospec
             if stage_idx == 0:
+                n_comb_stages -= 1
                 kls = FPDivStagesSetup # does n_comb_stages-1 calcs as well
 
             # needs to convert output to pipeend ispec