From: colepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0 Date: Sun, 22 Nov 2020 20:25:08 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~1680 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d2aed397cbf8f662bcf84f288f5e147ec3099e65;p=libreriscv.git --- diff --git a/HDL_workflow/ECP5_FPGA.mdwn b/HDL_workflow/ECP5_FPGA.mdwn index 743b58b47..2de8a773a 100644 --- a/HDL_workflow/ECP5_FPGA.mdwn +++ b/HDL_workflow/ECP5_FPGA.mdwn @@ -12,7 +12,7 @@ See Checklist based on above -* For god's sake make sure you get this right, ***quadruple*** check everything. +* For god's sake make sure you get this right, ***TRIPLE*** check everything. * ***DO*** make sure to ***only*** drive an input as an input, and to ***only*** drive an output as an output. @@ -57,7 +57,7 @@ Final steps for both FPGA boards: | Done? | Checklist Step | |---------|----------------| -| | Check each jumper wire connection between the corresponding pins on the FPGA and the STLINKv2 **four** times | +| | Check each jumper wire connection between the corresponding pins on the FPGA and the STLINKv2 **THREE** times | | | I don't know what's next, need to review with lkcl | ## Connecting the dots: