From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 19 May 2019 08:19:40 +0000 (+0100)
Subject: creating separate dependency cell which can be used for all 3 src1/src2/dest
X-Git-Tag: div_pipeline~2014
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d2b7dc9bf25e6659ce2932ed53d536d0f060a4f2;p=soc.git

creating separate dependency cell which can be used for all 3 src1/src2/dest
---

diff --git a/src/scoreboard/dependence_cell.py b/src/scoreboard/dependence_cell.py
index 1ae81b59..e448588a 100644
--- a/src/scoreboard/dependence_cell.py
+++ b/src/scoreboard/dependence_cell.py
@@ -24,15 +24,19 @@ class DepCell(Elaboratable):
         m = Module()
         m.submodules.l = l = SRLatch(sync=False) # async latch
 
+        # record current version of q in a sync'd register
+        cq = Signal() # resets to 0
+        m.d.sync += cq.eq(l.q)
+
         # reset on go HI, set on dest and issue
-        m.d.comb += dest_l.s.eq(self.issue_i & self.reg_i)
-        m.d.comb += dest_l.r.eq(self.go_i)
+        m.d.comb += l.s.eq(self.issue_i & self.reg_i)
+        m.d.comb += l.r.eq(self.go_i)
 
-        # FU "Forward Progress" (read out horizontally)
-        m.d.sync += self.fwdl_o.eq(l.q & self.reg_i)
+        # Function Unit "Forward Progress".
+        m.d.comb += self.fwd_o.eq((cq | l.q) & self.reg_i)
 
-        # Register File Select (read out vertically)
-        m.d.comb += self.rselo.eq(l.q & self.go_i)
+        # Register Select. Activated on go read/write and *current* latch set
+        m.d.comb += self.rsel_o.eq(cq & self.go_i)
 
         return m
 
@@ -88,12 +92,12 @@ class DependenceCell(Elaboratable):
         m.d.comb += src2_l.s.eq(self.issue_i & self.src2_i)
         m.d.comb += src2_l.r.eq(self.go_rd_i)
 
-        # FU "Forward Progress" (read out horizontally)
+        # FU "Forward Progress" (read out vertically)
         m.d.comb += self.dest_fwd_o.eq(dest_l.q & self.dest_i)
         m.d.comb += self.src1_fwd_o.eq(src1_l.q & self.src1_i)
         m.d.comb += self.src2_fwd_o.eq(src2_l.q & self.src2_i)
 
-        # Register File Select (read out vertically)
+        # Register File Select (read out horizontally)
         m.d.sync += self.dest_rsel_o.eq(dest_l.q & ~self.go_wr_i)
         m.d.sync += self.src1_rsel_o.eq(src1_l.q & ~self.go_rd_i)
         m.d.sync += self.src2_rsel_o.eq(src2_l.q & ~self.go_rd_i)