From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 14 Jun 2020 17:21:10 +0000 (+0100)
Subject: add link to uart
X-Git-Tag: convert-csv-opcode-to-binary~2439
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d92382167b931f0dd6f72bc88eef6321eaf1d17f;hp=cfe05eafa36f7b2febfd7df4f3ad189404f50148;p=libreriscv.git

add link to uart
---

diff --git a/shakti/m_class.mdwn b/shakti/m_class.mdwn
index 63e288b2a..a624b3eb4 100644
--- a/shakti/m_class.mdwn
+++ b/shakti/m_class.mdwn
@@ -211,8 +211,8 @@ TBD
 * 2x 1-lane [[SPI]]
 * 1x 4-lane (quad) [[QSPI]]
 * 4x SD/MMC (1x 1/2/4/8-bit, 3x 1/2/4-bit)
-* 2x full UART incl. CTS/RTS
-* 3x UART (TX/RX only)
+* 2x full [[UART]] incl. CTS/RTS
+* 3x [[UART]] (TX/RX only)
 * 3x [[I2C]] (in case of address clashes between peripherals)
 * 8080-style AT/XT/ATI MCU Bus Interface, with multiple (8x CS#) lines
 * 3x [[PWM]]-capable GPIO
diff --git a/shakti/m_class/UART.mdwn b/shakti/m_class/UART.mdwn
new file mode 100644
index 000000000..f4db6db74
--- /dev/null
+++ b/shakti/m_class/UART.mdwn
@@ -0,0 +1,3 @@
+# UART RTL
+
+* <https://git.m-labs.hk/M-Labs/HeavyX/src/branch/master/heavycomps/heavycomps/uart.py>