From: Michael Nolan <mtnolan2640@gmail.com>
Date: Thu, 26 Mar 2020 14:55:24 +0000 (-0400)
Subject: Add tests for subfic and neg
X-Git-Tag: div_pipeline~1623
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dbaa53d9c846b1ecf32516fa5abc274bbd40b3ca;p=soc.git

Add tests for subfic and neg
---

diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py
index 95e0d291..aadaf667 100644
--- a/src/soc/simulator/test_sim.py
+++ b/src/soc/simulator/test_sim.py
@@ -91,9 +91,11 @@ class DecoderTestCase(FHDLTestCase):
     def test_sub(self):
         lst = ["addi 1, 0, 0x1234",
                "addi 2, 0, 0x5678",
-               "subf 1, 1, 2"]
+               "subf 3, 1, 2",
+               "subfic 4, 1, 0x1337",
+               "neg 5, 1"]
         with Program(lst) as program:
-            self.run_test_program(program, [1, 2])
+            self.run_test_program(program, [1, 2, 3, 4, 5])
 
     def run_test_program(self, prog, reglist):
         simulator = InternalOpSimulator()