From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 26 Jul 2018 06:28:06 +0000 (+0100)
Subject: pep8 cleanup
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e1406e535ffa54aa50395739a07ee1e400e4559c;p=pinmux.git

pep8 cleanup
---

diff --git a/src/bsv/peripheral_gen/base.py b/src/bsv/peripheral_gen/base.py
index 8b9a469..d3bafad 100644
--- a/src/bsv/peripheral_gen/base.py
+++ b/src/bsv/peripheral_gen/base.py
@@ -1,5 +1,6 @@
 import types
 
+
 def li(txt, indent):
     indent = ' ' * indent
     istxt = False
@@ -279,7 +280,7 @@ else"""
 
     def extifinstance(self, name, count):
         return self._extifinstance(name, count, "",
-                                            "pinmux.peripheral_side.")
+                                   "pinmux.peripheral_side.")
 
 
 mkplic_rule = """\
@@ -291,7 +292,7 @@ rule rl_connect_{0}_to_plic_{2};
 endrule
 """
 
-axi_master_declarations= """\
+axi_master_declarations = """\
 typedef 0 Dmem_master_num;
 typedef 1 Imem_master_num;
 {0}
@@ -646,13 +647,13 @@ class PeripheralInterfaces(object):
 
         cnct = list(filter(None, cnct))
         ct = self.dma_count
-        _cnct    = ["rule rl_connect_interrupt_to_DMA;",
-                    "  Bit #(%d) lv_interrupt_to_DMA={" % ct]
+        _cnct = ["rule rl_connect_interrupt_to_DMA;",
+                 "  Bit #(%d) lv_interrupt_to_DMA={" % ct]
         spc = "                      "
         spcsep = ",\n" + spc
         cnct = _cnct + [spc + spcsep.join(cnct)]
         cnct.append("   };")
-        cnct.append("   dma.interrupt_from_peripherals(\n" + \
+        cnct.append("   dma.interrupt_from_peripherals(\n" +
                     "       lv_interrupt_to_DMA);")
         cnct.append("endrule;")
 
diff --git a/src/bsv/peripheral_gen/jtag.py b/src/bsv/peripheral_gen/jtag.py
index abd374f..d8e63de 100644
--- a/src/bsv/peripheral_gen/jtag.py
+++ b/src/bsv/peripheral_gen/jtag.py
@@ -9,10 +9,9 @@ class jtag(PBase):
     def extfastifinstance(self, name, count):
         return self._extifinstance(name, count, "_out", "", True)
 
-
     def fastifdecl(self, name, count):
         # YUK!
-        return "Ifc_jtagdtm jtag{0}_out;".format(count);
+        return "Ifc_jtagdtm jtag{0}_out;".format(count)
 
     def mkfast_peripheral(self):
         return """\
@@ -25,6 +24,7 @@ rule drive_tmp_scan_outs;
     jtag{0}.scan_out_5_i(1'b0);
 endrule
 """
+
     def axi_slave_name(self, name, ifacenum, typ=''):
         return ''
 
diff --git a/src/bsv/peripheral_gen/quart.py b/src/bsv/peripheral_gen/quart.py
index 51e1803..ec38fa6 100644
--- a/src/bsv/peripheral_gen/quart.py
+++ b/src/bsv/peripheral_gen/quart.py
@@ -14,7 +14,7 @@ class quart(PBase):
                "method Bit#(1) %s;" % self.irq_name()
 
     def get_clock_reset(self, name, count):
-        return "slow_clock,slow_reset" # XXX TODO: change to uart_clock/reset
+        return "slow_clock,slow_reset"  # XXX TODO: change to uart_clock/reset
 
     def num_axi_regs32(self):
         return 8
diff --git a/src/bsv/pinmux_generator.py b/src/bsv/pinmux_generator.py
index 8b23f0e..03ee609 100644
--- a/src/bsv/pinmux_generator.py
+++ b/src/bsv/pinmux_generator.py
@@ -126,11 +126,12 @@ def write_slow(slow, slowt, p, ifaces, iocells):
                                     numsloirqs, ifacedef,
                                     inst2))
 
+
 def write_soc(soc, soct, p, ifaces, iocells):
     """ write out the soc.bsv file.
         joins all the peripherals together as AXI Masters
     """
-    ifaces.fastbusmode = True # side-effects... shouldn't really do this
+    ifaces.fastbusmode = True  # side-effects... shouldn't really do this
     with open(soct) as bsv_file:
         soct = bsv_file.read()
     imports = ifaces.slowimport()
@@ -152,13 +153,9 @@ def write_soc(soc, soct, p, ifaces, iocells):
     num_dmachannels = ifaces.num_dmachannels()
     with open(soc, "w") as bsv_file:
         bsv_file.write(soct.format(imports, ifdecl, mkfast,
-                            slavedecl, mastdecl, mkcon,
-                            inst, dma, num_dmachannels,
-                            #'', '' #regdef, slavedecl,
-                            #'', mkslow, #fnaddrmap, mkslow, mkcon, mkcellcon,
-                            #pincon, inst, mkplic,
-                            #numsloirqs, ifacedef))
-                                  ))
+                                   slavedecl, mastdecl, mkcon,
+                                   inst, dma, num_dmachannels,
+                                   ))
 
 
 def write_bus(bus, p, ifaces):
diff --git a/src/spec/interfaces.py b/src/spec/interfaces.py
index b35e935..684173e 100644
--- a/src/spec/interfaces.py
+++ b/src/spec/interfaces.py
@@ -98,7 +98,7 @@ class Pinouts(object):
 
     def setganged(self, fname, grp):
         grp = map(lambda x: x[:-1], grp)
-        if not self.ganged.has_key(fname):
+        if fname not in self.ganged:
             self.ganged[fname] = []
         self.ganged[fname] += grp