From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 10 Aug 2019 10:18:09 +0000 (+0100)
Subject: {x}{y} in verilog means x occurrences of y
X-Git-Tag: ls180-24jan2020~540
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e95cc4f879bf198378205a2d01852e1db5b38c32;p=ieee754fpu.git

{x}{y} in verilog means x occurrences of y
---

diff --git a/src/ieee754/fpdiv/mulAddRecFN.py b/src/ieee754/fpdiv/mulAddRecFN.py
index 4b02667d..49dd1469 100644
--- a/src/ieee754/fpdiv/mulAddRecFN.py
+++ b/src/ieee754/fpdiv/mulAddRecFN.py
@@ -172,8 +172,9 @@ class mulAddRecFNToRaw_preMul(Elaboratable):
                                   sigSumWidth - 1)),
             # XXX check! {doSubMags ? ~sigC : sigC,
             #            {(sigSumWidth - sigWidth + 2){doSubMags}}};
-            extComplSigC.eq(Cat((sigSumWidth - sigWidth + 2){doSubMags}},
-                                Mux(doSubMags, ~sigC, sigC))),
+            sc = [doSubMags] * (sigSumWidth - sigWidth + 2) + \
+                                [Mux(doSubMags, ~sigC, sigC)]
+            extComplSigC.eq(Cat(*sc))
             # XXX check!  nmigen doesn't have >>> operator, only >>
             mainAlignedSigC.eq(extComplSigC >>> CAlignDist),
             grainAlignedSigC.eq(sigC<<CGrainAlign),