From: Andrew Waterman <andrew@sifive.com>
Date: Sun, 8 Jan 2017 02:03:16 +0000 (-0800)
Subject: Only allow SIP.SSIP to be toggled if the interrupt is delegated
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e9e30598e08e4f162b523f9ef07f1510f3cfe0a6;p=riscv-isa-sim.git

Only allow SIP.SSIP to be toggled if the interrupt is delegated
---

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 75f4002..7417acf 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -374,7 +374,7 @@ void processor_t::set_csr(int which, reg_t val)
       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
     }
     case CSR_SIP: {
-      reg_t mask = MIP_SSIP;
+      reg_t mask = MIP_SSIP & state.mideleg;
       return set_csr(CSR_MIP, (state.mip & ~mask) | (val & mask));
     }
     case CSR_SIE: